Alternatives and similar repositories for vivado-git

Users that are interested in vivado-git are comparing it to the libraries listed below

• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆264Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆568Updated 2 months ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆390Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆436Updated last week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆267Updated last year
• Digilent / vivado-boards
  ☆444Updated 5 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆434Updated 2 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆171Updated this week
• alexforencich / verilog-uart
  Verilog UART
  ☆490Updated 3 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆353Updated last year
• jamieiles / uart
  Verilog UART
  ☆172Updated 12 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆629Updated this week
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆624Updated 3 months ago
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆810Updated 3 months ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆242Updated this week
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆304Updated last year
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆138Updated last year
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆399Updated last month
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆347Updated last week
• Xilinx / Vivado-Design-Tutorials
  ☆211Updated last week
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆252Updated 5 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆475Updated 3 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆232Updated 2 years ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆397Updated 3 weeks ago
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆246Updated last month
• VLSI-EDA / PoC
  IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…
  ☆580Updated 4 years ago
• svunit / svunit
  ☆201Updated 3 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆275Updated 5 years ago
• Digilent / vivado-library
  ☆618Updated 11 months ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆813Updated 3 years ago