sjj-star / automatically-generate-Wallace-Tree-VerilogHDL-codeLinks
本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
☆25Updated 2 years ago
Alternatives and similar repositories for automatically-generate-Wallace-Tree-VerilogHDL-code
Users that are interested in automatically-generate-Wallace-Tree-VerilogHDL-code are comparing it to the libraries listed below
Sorting:
- ☆33Updated 6 years ago
- ☆10Updated 4 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆32Updated 8 months ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆48Updated 9 months ago
- Implement a bitonic sorting network on FPGA☆44Updated 3 years ago
- SoC Based on ARM Cortex-M3☆32Updated 3 weeks ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- ☆65Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- Open IP in Hardware Description Language.☆23Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆49Updated 6 years ago
- ☆28Updated 4 years ago
- ☆27Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆52Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- AXI总线连接器☆97Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last week
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- ☆20Updated 2 years ago
- syn script for DC Compiler☆13Updated 3 years ago