USB2.0 Verilog
☆20Apr 21, 2019Updated 7 years ago
Alternatives and similar repositories for USB_Ctrl
Users that are interested in USB_Ctrl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- Delta Sigma DAC FPGA☆47Feb 21, 2025Updated last year
- Hardware Description Language Translator☆17Jun 9, 2026Updated last month
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- OreSat hardware for high speed data communications using 2.4 GHz WiFi.☆17Jul 13, 2026Updated last week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 6 years ago
- FOR FRESHMAN IN NUDT CORE LAB RESEARCH AND CODING TOOLS☆10Jun 19, 2022Updated 4 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- ID card location and identification between back and front sides using OpenCV☆11Dec 6, 2023Updated 2 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 6 years ago
- Open Source Windows UAC2 driver☆21Feb 24, 2013Updated 13 years ago
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- This repository contains source code for Universal boot loader This repository contains source code for Universal boot loader for use wit…☆12Aug 19, 2025Updated 11 months ago
- sx1280基本收发☆10Jul 24, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆36May 28, 2021Updated 5 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Super Audio CD ISO-Image decoder addon☆18Jul 11, 2026Updated last week
- A simple implementation of the Karatsuba multiplication algorithm☆12Apr 2, 2025Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 7 years ago
- USB2.0 Device Controller IP Core☆17Aug 18, 2023Updated 2 years ago
- Human Protein Atlas image classification competition☆13May 22, 2023Updated 3 years ago
- 2021 Xilinx China Winter Camp☆11Mar 12, 2021Updated 5 years ago
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Code for Disambiguating Monocular Depth Estimation with a Single Transient☆12Sep 8, 2020Updated 5 years ago
- ☆12Jan 19, 2019Updated 7 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- FFmpeg with Cedrus264 for H3 (Cedrus264 HW Encoder)☆16Aug 17, 2016Updated 9 years ago
- USB capture IP☆26Jun 6, 2020Updated 6 years ago
- fork from https://gitee.com/crouchggj/STM32F4_USB_SoundCard☆17Aug 3, 2019Updated 6 years ago
- PyTorch Learning Tutorial in Chinese☆10Apr 15, 2018Updated 8 years ago
- 一个基于 TradingAgents 多智能体量化分析框架的现代化 Web 版本，同时支持美股、港股和A股☆15Updated this week
- VHDL source file project for a hardware in the loop simulation of a permanen magnet motor with field oriented control design☆12Nov 22, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 7 years ago
- Ultra96 PYNQ入门之一次简单的总结☆14May 21, 2020Updated 6 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆22Jul 10, 2026Updated last week
- My implementation of pid tunner following TI's InstaSPIN guide.☆16Jul 10, 2020Updated 6 years ago
- 模型量化工程 Base pretrained models and datasets in pytorch (MNIST, SVHN, CIFAR10, CIFAR100, STL10, AlexNet, VGG16, VGG19, ResNet, Inception,…☆12Aug 3, 2018Updated 7 years ago
- ☆14Oct 20, 2015Updated 10 years ago
- Cheapest UAC2 using STM32F407+USB3300☆22Feb 26, 2025Updated last year