USB2.0 Verilog
☆20Apr 21, 2019Updated 7 years ago
Alternatives and similar repositories for USB_Ctrl
Users that are interested in USB_Ctrl are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆16Jan 13, 2015Updated 11 years ago
- Delta Sigma DAC FPGA☆47Feb 21, 2025Updated last year
- Hardware Description Language Translator☆17Aug 7, 2026Updated last month
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- USB 2.0 Device IP Core☆75Oct 1, 2017Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 13 years ago
- USB1.1 Host Controller + PHY☆18Aug 4, 2021Updated 5 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 10 years ago
- LMS sound filtering by Verilog☆43Apr 5, 2020Updated 6 years ago
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- Open Source Windows UAC2 driver☆21Feb 24, 2013Updated 13 years ago
- This repository contains source code for Universal boot loader This repository contains source code for Universal boot loader for use wit…☆12Aug 19, 2025Updated last year
- USB 1.1 Host and Function IP core☆27Jul 17, 2014Updated 12 years ago
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated last month
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 6 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆14Mar 30, 2023Updated 3 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆19Apr 17, 2021Updated 5 years ago
- Super Audio CD ISO-Image decoder addon☆19Aug 23, 2026Updated 3 weeks ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- ☆11Jun 28, 2020Updated 6 years ago
- 简单易用的微信小程序倒计时库☆15May 15, 2018Updated 8 years ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Human Protein Atlas image classification competition☆13May 22, 2023Updated 3 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- Code for Disambiguating Monocular Depth Estimation with a Single Transient☆12Sep 8, 2020Updated 6 years ago
- ☆12Jan 19, 2019Updated 7 years ago
- FIR Filter in Verilog☆15Nov 17, 2019Updated 6 years ago
- Systolic Array implementation for ASIC Course☆15Nov 26, 2023Updated 2 years ago
- fork from https://gitee.com/crouchggj/STM32F4_USB_SoundCard☆17Aug 3, 2019Updated 7 years ago
- PyTorch Learning Tutorial in Chinese☆10Apr 15, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 一个基于 TradingAgents 多智能体量化分析框架的现代化 Web 版本,同时支持美股、港股和A股☆14Sep 11, 2026Updated last week
- VHDL source file project for a hardware in the loop simulation of a permanen magnet motor with field oriented control design☆13Nov 22, 2022Updated 3 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆17Oct 21, 2020Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆36May 28, 2021Updated 5 years ago
- 16 bit serial multiplier in SystemVerilog☆13Oct 13, 2018Updated 7 years ago
- Ultra96 PYNQ入门之一次简单的总结☆14May 21, 2020Updated 6 years ago