maxs-well / USB_CtrlLinks
USB2.0 Verilog
☆19Updated 6 years ago
Alternatives and similar repositories for USB_Ctrl
Users that are interested in USB_Ctrl are comparing it to the libraries listed below
Sorting:
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆77Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆42Updated 11 years ago
- 常用Verilog 模块☆20Updated 5 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆49Updated 5 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- FPGA 同步FIFO与异步FIFO☆31Updated 6 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆22Updated last week
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- JPEG Encoder Verilog☆77Updated 3 years ago
- USB -> AXI Debug Bridge☆40Updated 4 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆75Updated 3 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- 软件无线电,使用FPGA进行正交解调。☆22Updated 6 years ago
- USB2.0 Device Controller IP Core☆13Updated 2 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Updated 5 years ago
- ☆38Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- Implementation of the PCIe physical layer☆56Updated 3 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- 【例程】国产高云FPGA 开发板及其工程☆38Updated last year
- SPI通信实现FLASH读写☆16Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆68Updated 4 years ago
- AXI Interface Nand Flash Controller (Sync mode)☆97Updated last year