gagan405 / WallTree
A VHDL code generator for wallace tree multiplier
☆9Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for WallTree
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆14Updated 8 months ago
- MathLib DAC 2023 version☆12Updated last year
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 5 years ago
- A padring generator for ASICs☆22Updated last year
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- USB virtual model in C++ for Verilog☆28Updated last month
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆19Updated 4 years ago
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago
- ☆19Updated last year
- Analog and power building blocks for sky130 pdk☆20Updated 3 years ago
- ☆36Updated 2 years ago
- SAR ADC on tiny tapeout☆35Updated 2 weeks ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆40Updated 7 months ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆11Updated 3 years ago
- ☆19Updated 3 years ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆28Updated 3 years ago
- ☆33Updated last year
- Summer School Week 1 & 2 repo☆11Updated 2 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆25Updated 11 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- Top level for the November shuttle☆11Updated 3 years ago
- ☆15Updated 2 weeks ago
- A RISC-V processor☆13Updated 5 years ago
- ☆39Updated last year
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 3 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 4 months ago