Alternatives and similar repositories for PCIe_Scrambler

Users that are interested in PCIe_Scrambler are comparing it to the libraries listed below

• eminfedar / fedar-f1-rv64im
  5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
  ☆214Updated 4 years ago
• kirbyydoge / kasirga_gok_2023
  Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı
  ☆17Updated 2 years ago
• TUTEL-TUBITAK / TEKNOFEST_2023_Cip_Tasarim_Yarismasi
  Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…
  ☆20Updated 2 years ago
• koraykarakurt / FPGA-from-Zero-to-Hero
  Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
  ☆36Updated 5 months ago
• yusfux / KASIRGA-GUN
  KASIRGA-GUN | RV32IMCX
  ☆11Updated last year
• kirbyydoge / kasirga_2023
  Kasırga Sayısal Görüntü İşleme Kategorisi Hızlandırıcı Tasarımı
  ☆14Updated 2 years ago
• mbaykenar / apis_anatolia
  "Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
  ☆112Updated last year
• muhammedkocaoglu / mystic_riscv64
  64-bit RISC-V processor
  ☆16Updated 3 years ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆30Updated last year
• vinayrayapati / iiitb_rv32i
  ☆14Updated 3 years ago
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆19Updated 2 years ago
• chinthacharan / DV-Interview-Prep-Guide
  Design Verification Engineer interview preparation guide.
  ☆41Updated 5 months ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆15Updated last year
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆12Updated 5 months ago
• muhammedkocaoglu / SystemVerilog-Tutorials
  SystemVerilog derslerinde yazdığım kodları içermektedir.
  ☆15Updated 2 years ago
• eminfedar / fedar-e1-rv32i
  5-Stage Pipelined RV32I RISC-V Core design in Verilog-2005. It has 32 GPIO pins and it is FPGA synthesible.
  ☆24Updated 3 years ago
• Nirvan007 / Analog_Electronics
  This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…
  ☆25Updated last year
• emrealci / FPGA-Verilog
  Practices related to the fundamental level of the programming language Verilog.
  ☆12Updated 2 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• Learning-Chips-Lab / OpenEye
  The Open Source Hardware Accelerator for Efficient Neural Network Inference
  ☆48Updated this week
• vsdip / vsdfpga_labs
  ☆13Updated 8 months ago
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated 2 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆36Updated 2 years ago
• Tooba12322 / RTL_Designs
  ☆15Updated last year
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆47Updated last year
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆27Updated last year