baselkelziye / PCIe_ScramblerView external linksLinks
PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambling rules. Implemented in Verilog, Suitable for PIPE, Supports Enable/Disable Feature for debug purposes
☆15Jul 5, 2025Updated 7 months ago
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