PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambling rules. Implemented in Verilog, Suitable for PIPE, Supports Enable/Disable Feature for debug purposes
☆18Jul 5, 2025Updated 9 months ago
Alternatives and similar repositories for PCIe_Scrambler
Users that are interested in PCIe_Scrambler are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PCIe System Verilog Verification Environment developed for PCIe course☆15Mar 26, 2024Updated 2 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- Library of FPGA architectures☆31Updated this week
- PCIE 5.0 Graduation project (Verification Team)☆106Jan 27, 2024Updated 2 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 13 years ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆15Mar 9, 2026Updated last month
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆64Updated this week
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 8 months ago
- SGMII☆14Jul 17, 2014Updated 11 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- A hardware component library developed with ROHD.☆112Mar 6, 2026Updated last month
- USB2.0 Device Controller IP Core☆16Aug 18, 2023Updated 2 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- 2D Systolic Array Multiplier☆26Jan 27, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Wishbone bridge over SPI☆11Nov 13, 2019Updated 6 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- Implementation of the PCIe physical layer☆63Jul 11, 2025Updated 9 months ago
- Precompiled firmware binaries for testing ESP32 chips on Wokwi☆10Apr 12, 2026Updated last week
- PCIe analyzer experiments☆68May 21, 2020Updated 5 years ago
- GUI for SymbiYosys☆17Oct 13, 2025Updated 6 months ago
- FPGA code for NeTV2☆16Dec 3, 2018Updated 7 years ago
- Ethernet-MAC System verilog☆12May 28, 2018Updated 7 years ago
- Project Trellis database☆14Sep 15, 2025Updated 7 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Space CACD☆11Oct 16, 2019Updated 6 years ago
- open-source Ethenet media access controller for Ariane on Genesys-2☆19Jun 24, 2019Updated 6 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- A mirror of http://mayhewlabs.com/webGerber/☆13Oct 7, 2019Updated 6 years ago
- Interfaz directa con teclados USB en Verilog con control de los Leds de teclado y conversión a PS/2.☆18Feb 26, 2022Updated 4 years ago
- Project Peppercorn GateMate Test Cases☆15Feb 25, 2026Updated last month
- A collection of HDL cores written in MyHDL.☆12Oct 28, 2015Updated 10 years ago
- ☆15Jan 25, 2026Updated 2 months ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆12Jun 4, 2021Updated 4 years ago
- Linux kernel driver for the Exar xr21v141x "vizzini" UART☆10Jul 2, 2015Updated 10 years ago
- A Javascript library for generating blocks for the ICEstudio FPGA development environment☆10Jul 31, 2018Updated 7 years ago
- FPGA Portable Music Generator☆11Aug 1, 2018Updated 7 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- gateware for the main fpga, including a hispi decoder and image processing☆13Sep 27, 2018Updated 7 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆19Oct 23, 2023Updated 2 years ago