Lightelligence / rules_verilog

Related projects ⓘ

Alternatives and complementary repositories for rules_verilog

• hdl / bazel_rules_hdl
  Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…
  ☆116Updated this week
• chipsalliance / fpga-interchange-schema
  ☆51Updated 2 years ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆46Updated 8 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆51Updated 3 weeks ago
• Kuree / hgdb
  Hardware generator debugger
  ☆71Updated 9 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆33Updated 4 years ago
• kkiningh / rules_verilator
  Bazel build rules for Verilator
  ☆24Updated 7 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated last week
• mattvenn / instrumented_adder
  Instrumenting adders to measure speed
  ☆13Updated 2 years ago
• Raamakrishnan / verilog-filelist-parser
  A Verilog Filelist parser in Rust
  ☆9Updated 2 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆45Updated last week
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• pieter3d / simview
  ☆76Updated 8 months ago
• byuccl / bfat
  Bitstream Fault Analysis Tool
  ☆13Updated last year
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆40Updated 3 months ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆42Updated last month
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆30Updated this week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆42Updated 7 months ago
• povik / yosys-slang
  slang-based frontend for Yosys
  ☆41Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆101Updated 8 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆93Updated this week
• agoessling / rules_vivado
  Bazel rules for Xilinx Vivado
  ☆18Updated 2 years ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆105Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆81Updated 5 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆67Updated last year
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆78Updated last month
• chipsalliance / uvm-verilator
  ☆73Updated last year