Lightelligence / rules_verilog
Bazel build rules for compiling Verilog
☆21Updated 11 months ago
Alternatives and similar repositories for rules_verilog:
Users that are interested in rules_verilog are comparing it to the libraries listed below
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆127Updated this week
- Bazel build rules for Verilator☆24Updated 10 months ago
- ☆54Updated 2 years ago
- Hardware generator debugger☆73Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆55Updated last month
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A SystemVerilog source file pickler.☆54Updated 4 months ago
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- Bazel rules for Xilinx Vivado☆18Updated 2 years ago
- A Verilog Filelist parser in Rust☆10Updated 2 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆35Updated 3 weeks ago
- An automatic clock gating utility☆43Updated 7 months ago
- Instrumenting adders to measure speed☆13Updated 2 years ago
- Running Python code in SystemVerilog☆67Updated 7 months ago
- Mutation Cover with Yosys (MCY)☆81Updated last week
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated 4 months ago
- ☆36Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- ☆31Updated last year
- A command-line tool for displaying vcd waveforms.☆51Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 9 months ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆90Updated this week
- ☆77Updated 11 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆52Updated last week
- Bitstream Fault Analysis Tool☆13Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 7 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- SystemVerilog frontend for Yosys☆74Updated this week
- Equivalence checking with Yosys☆40Updated last week