oprecomp / flexfloatLinks
C library for the emulation of reduced-precision floating point types
☆54Updated 2 years ago
Alternatives and similar repositories for flexfloat
Users that are interested in flexfloat are comparing it to the libraries listed below
Sorting:
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆127Updated last year
- A Tiny Processor Core☆114Updated 6 months ago
- Visual Simulation of Register Transfer Logic☆109Updated 5 months ago
- Debuggable hardware generator☆70Updated 2 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆108Updated 4 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- Floating point modules for CHISEL☆32Updated 11 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆45Updated 9 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- PACoGen: Posit Arithmetic Core Generator☆76Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- ☆26Updated 5 years ago
- Pulp virtual platform☆24Updated 6 months ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated last year
- pulp_soc is the core building component of PULP based SoCs☆81Updated 10 months ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- Algorithmic C Datatypes☆134Updated 2 weeks ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated last week
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆28Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago
- Python Model of the RISC-V ISA☆62Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆26Updated 7 years ago