oprecomp / flexfloat

Related projects: ⓘ

• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆34Updated 5 months ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆87Updated 10 months ago
• pulp-platform / RVfplib
  Optimized RISC-V FP emulation for 32-bit processors
  ☆31Updated 3 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆63Updated 5 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆66Updated last year
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆35Updated last year
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆27Updated 9 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆56Updated 5 years ago
• fbrosser / DSP48E1-FP
  Project aimed at implementing floating point operators using the DSP48E1 slice.
  ☆24Updated 11 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆30Updated 9 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆74Updated 3 weeks ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 2 months ago
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆50Updated 5 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆45Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆56Updated 3 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆86Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated 10 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆55Updated this week
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆21Updated 4 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆55Updated 7 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆38Updated 4 years ago
• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆87Updated 5 months ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆55Updated last month
• leos313 / DOOM_FPGA
  Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
  ☆16Updated 4 years ago
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆41Updated last year
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆40Updated 5 years ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆40Updated 6 years ago