Minres / CoreDSLLinks
Xtext project to parse CoreDSL files
☆20Updated 6 months ago
Alternatives and similar repositories for CoreDSL
Users that are interested in CoreDSL are comparing it to the libraries listed below
Sorting:
- ☆87Updated last year
- A hardware synthesis framework with multi-level paradigm☆40Updated 7 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated 2 weeks ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆155Updated 2 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 10 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Benchmarks for Accelerator Design and Customized Architectures☆128Updated 5 years ago
- CGRA Compilation Framework☆86Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆106Updated 3 months ago
- ☆58Updated 2 years ago
- CGRA framework with vectorization support.☆34Updated last week
- high-performance RTL simulator☆172Updated last year
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆125Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆57Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Next generation CGRA generator☆113Updated last week
- ☆92Updated last year
- ☆47Updated last month
- RiVEC Bencmark Suite☆119Updated 8 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆154Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆191Updated 5 years ago
- The Task Parallel System Composer (TaPaSCo)☆111Updated 3 months ago