Xtext project to parse CoreDSL files
☆23Jul 22, 2026Updated 2 weeks ago
Alternatives and similar repositories for CoreDSL
Users that are interested in CoreDSL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆25Jul 31, 2026Updated last week
- TUM EI7402 SystemC laboratory assignments☆11Aug 10, 2021Updated 4 years ago
- Scalable Interface for RISC-V ISA Extensions☆26Jul 22, 2026Updated 2 weeks ago
- Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends☆34May 20, 2026Updated 2 months ago
- 这是一个针对所有人的C编程教程。This is a C programming tutorial for real beginningers.☆11Oct 29, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Online documentation can be found at https://minres.github.io/SCViewer/☆22Apr 10, 2026Updated 4 months ago
- Tools and APIs to develop weavers for the LARA language (LARA Compiler, LARA Interpreter, Weaver Generator, etc...)☆16Updated this week
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 5 years ago
- CV32E40X Design-Verification environment☆18Jun 2, 2026Updated 2 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- Filelist generator☆21Jun 23, 2026Updated last month
- Example for running IREE in a bare-metal Arm environment.☆43Feb 24, 2026Updated 5 months ago
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated last year
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 3 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Yet another implementation of TI C6x DSP simulator☆11Jan 16, 2014Updated 12 years ago
- ☆21Jul 18, 2021Updated 5 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 9 months ago
- ☆17Sep 14, 2023Updated 2 years ago
- A C-family AST implementation designed to be an IR for DSL compilers.☆17Jul 6, 2017Updated 9 years ago
- ☆19Jul 26, 2024Updated 2 years ago
- OpenTestability is an open-source tool for structural analysis of digital circuits, enabling computation of SCOAP metrics, Controllibilit…☆20Updated this week
- ☆10Dec 17, 2025Updated 7 months ago
- Helper of yaml file generation from single master yaml file.☆10Mar 17, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆33Jan 7, 2025Updated last year
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆20Jul 29, 2021Updated 5 years ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆16Jun 29, 2026Updated last month
- Research about dataflow architecture☆15Nov 30, 2023Updated 2 years ago
- SQL Optimizations using MLIR☆12Apr 5, 2020Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- ☆36Jul 13, 2026Updated 3 weeks ago
- HDL Obfuscator☆12May 13, 2021Updated 5 years ago
- Code templates to get started experimenting with the RISC-V LLVM toolchain☆14Nov 25, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ET Accelerator Firmware and Runtime☆49Jul 17, 2026Updated 3 weeks ago
- A DAG processor and compiler for a tree-based spatial datapath.☆16Aug 24, 2022Updated 3 years ago
- A git subcommand to apply skeleton repository continuously☆15Updated this week
- JSON5 parser for Ruby☆18Jun 22, 2026Updated last month
- Administrative repository for the Integrated Matrix Extension Task Group☆37Jul 27, 2026Updated 2 weeks ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 12 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆111Jul 28, 2026Updated last week