Xtext project to parse CoreDSL files
☆23Apr 29, 2026Updated 2 months ago
Alternatives and similar repositories for CoreDSL
Users that are interested in CoreDSL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization☆25Jun 15, 2026Updated last month
- TUM EI7402 SystemC laboratory assignments☆11Aug 10, 2021Updated 4 years ago
- An open-source implementation of the VADL processor description language.☆52Updated this week
- Scalable Interface for RISC-V ISA Extensions☆26Jun 9, 2026Updated last month
- ATNwalk is a grammar-based input generator for fuzzing and other evolutionary algorithms. It relies on binary-level mutations to bit sequ…☆11Dec 10, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 这是一个针对所有人的C编程教程。This is a C programming tutorial for real beginningers.☆10Oct 29, 2021Updated 4 years ago
- Example for running IREE in a bare-metal Arm environment.☆43Feb 24, 2026Updated 4 months ago
- Online documentation can be found at https://minres.github.io/SCViewer/☆22Apr 10, 2026Updated 3 months ago
- Tools and APIs to develop weavers for the LARA language (LARA Compiler, LARA Interpreter, Weaver Generator, etc...)☆16Updated this week
- A RISC-V RV32 model ready for SMT program synthesis.☆12Jun 23, 2021Updated 5 years ago
- CV32E40X Design-Verification environment☆16Jun 2, 2026Updated last month
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆90Apr 1, 2026Updated 3 months ago
- Filelist generator☆21Jun 23, 2026Updated 3 weeks ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 11 months ago
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 9 months ago
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 2 months ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆16Jun 29, 2026Updated 3 weeks ago
- Yet another implementation of TI C6x DSP simulator☆11Jan 16, 2014Updated 12 years ago
- ☆15Updated this week
- A C-family AST implementation designed to be an IR for DSL compilers.☆17Jul 6, 2017Updated 9 years ago
- ☆13Oct 12, 2016Updated 9 years ago
- OpenTestability is an open-source tool for structural analysis of digital circuits, enabling computation of SCOAP metrics, Controllibilit…☆20Jul 13, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆10Dec 17, 2025Updated 7 months ago
- ☆33Jan 7, 2025Updated last year
- Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.☆20Jul 29, 2021Updated 4 years ago
- Helper of yaml file generation from single master yaml file.☆10Mar 17, 2020Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- ☆35Jul 13, 2026Updated last week
- SQL Optimizations using MLIR☆12Apr 5, 2020Updated 6 years ago
- HDL Obfuscator☆12May 13, 2021Updated 5 years ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆104Oct 6, 2025Updated 9 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ET Accelerator Firmware and Runtime☆47Updated this week
- The purpose of the repo is to support CORE-V Wally architectural verification☆19Nov 11, 2025Updated 8 months ago
- Code templates to get started experimenting with the RISC-V LLVM toolchain☆14Nov 25, 2018Updated 7 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆16Aug 24, 2022Updated 3 years ago
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- A git subcommand to apply skeleton repository continuously☆15Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆110May 22, 2026Updated last month