A collection of commonly asked RTL design interview questions
☆39May 2, 2017Updated 8 years ago
Alternatives and similar repositories for hw_interview_questions
Users that are interested in hw_interview_questions are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital Design verilog tricky problems having industry standards☆29Jul 30, 2020Updated 5 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆22Nov 21, 2020Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- For aspiring hardware engineers out there.☆84Mar 16, 2025Updated last year
- Fundamental analog circuit designs to kick start and embark the journey in the world of IC design.☆33Aug 31, 2023Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Neural Markov Logic Networks☆13Feb 14, 2022Updated 4 years ago
- Full Arduino based WIFI controlled drone. Build with single PCB.☆12Dec 8, 2020Updated 5 years ago
- coreless esp32 controlled drone☆10Mar 17, 2023Updated 3 years ago
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- An implementation of the Advanced Encryption Standard (AES) encryption algorithm using Verilog supporting AES-128, AES-192, and AES-256 e…☆12Jun 7, 2025Updated 9 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...☆31Dec 9, 2021Updated 4 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago
- ☆11Jun 19, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- UART serial interface on DE0-Nano☆10May 24, 2015Updated 10 years ago
- This is a tutorial on standard digital design flow☆85May 24, 2021Updated 4 years ago
- ☆10Aug 20, 2019Updated 6 years ago
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆17Dec 16, 2017Updated 8 years ago
- Firmware / software / Verilog for the Photon camera☆15Mar 20, 2026Updated last week
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 2 months ago
- Hardware accelerated AES Encryption for ESP32☆22May 2, 2021Updated 4 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Feb 26, 2025Updated last year
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆56Nov 16, 2023Updated 2 years ago
- SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions☆21Dec 1, 2024Updated last year
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Jan 16, 2026Updated 2 months ago
- Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...☆55Nov 7, 2021Updated 4 years ago
- Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA☆12Mar 29, 2018Updated 8 years ago
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆28Feb 16, 2026Updated last month
- ☆12Aug 12, 2022Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Processor support packages☆20Feb 2, 2021Updated 5 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- 100 Days of RTL☆408Aug 15, 2024Updated last year
- 丁建均老師的"時頻分析和小波轉換"作業(TFW)☆11Jan 18, 2024Updated 2 years ago
- ☆17Jan 28, 2018Updated 8 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- SystemVerilog Tutorial☆201Mar 7, 2026Updated 3 weeks ago