pengwubj / hw_interview_questionsLinks
A collection of commonly asked RTL design interview questions
☆35Updated 8 years ago
Alternatives and similar repositories for hw_interview_questions
Users that are interested in hw_interview_questions are comparing it to the libraries listed below
Sorting:
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆109Updated 10 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆100Updated 2 years ago
- ☆166Updated 3 years ago
- VIP for AXI Protocol☆155Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆67Updated 3 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆132Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆85Updated last year
- ☆50Updated 4 years ago
- UVM and System Verilog Manuals☆45Updated 6 years ago
- SystemVerilog VIP for AMBA APB protocol☆79Updated 3 years ago
- This is the repository for the IEEE version of the book☆74Updated 5 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆36Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆63Updated 2 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆30Updated 2 months ago
- Network on Chip Implementation written in SytemVerilog☆192Updated 3 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆109Updated 11 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆24Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆92Updated 6 years ago
- ☆16Updated last year
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆21Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- Some useful documents of Synopsys☆90Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆82Updated 7 years ago
- UVM examples and projects☆147Updated 4 months ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆155Updated 5 years ago