pengwubj / hw_interview_questionsLinks
A collection of commonly asked RTL design interview questions
☆32Updated 8 years ago
Alternatives and similar repositories for hw_interview_questions
Users that are interested in hw_interview_questions are comparing it to the libraries listed below
Sorting:
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- ☆47Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆109Updated 11 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆106Updated 8 months ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆32Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆53Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆65Updated 2 years ago
- VIP for AXI Protocol☆148Updated 3 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- AXI DMA 32 / 64 bits☆120Updated 11 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆21Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆174Updated 2 weeks ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆155Updated 5 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated last year
- This is the repository for the IEEE version of the book☆71Updated 4 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- ☆165Updated 3 years ago
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆24Updated 2 weeks ago
- Some useful documents of Synopsys☆83Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆152Updated last year
- UVM examples and projects☆143Updated 2 months ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 4 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆94Updated 2 years ago
- UART design in SV and verification using UVM and SV☆49Updated 5 years ago