Alternatives and similar repositories for hw_interview_questions:

Users that are interested in hw_interview_questions are comparing it to the libraries listed below

• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆29Updated 5 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆33Updated 9 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆39Updated last year
• shubhi704 / APB-Protocol
  ☆41Updated 3 years ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆20Updated 3 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆39Updated 6 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆57Updated 11 months ago
• amamory-verification / uvm-basics
  my UVM training projects
  ☆31Updated 6 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆23Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆22Updated last year
• Devipriya1921 / VSDBabySoC_ICC2
  ☆10Updated 2 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆67Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• IEEE-NITK / VLSI_design-of-RISC
  IEEE Executive project for the year 2021-2022
  ☆9Updated 2 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆57Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆53Updated 8 years ago
• mihir8181 / VerilogHDL-Codes
  Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
  ☆34Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 7 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆53Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆36Updated 2 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆82Updated 5 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆62Updated 5 years ago
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆14Updated 2 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 7 months ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆16Updated 10 months ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆58Updated last year
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆46Updated 2 months ago