addisonElliott / SCIC
Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.
☆14Updated 6 years ago
Alternatives and similar repositories for SCIC:
Users that are interested in SCIC are comparing it to the libraries listed below
- Extensible FPGA control platform☆56Updated last year
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆21Updated 5 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆15Updated 5 years ago
- Framework Open EDA Gui☆63Updated last month
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆17Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆27Updated 3 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago
- DDR4 Simulation Project in System Verilog☆33Updated 10 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆30Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆14Updated 4 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆30Updated 3 years ago
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 5 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- This project shows the design process of the main blocks of a typical RX frontend system.☆22Updated 4 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆16Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆32Updated this week
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Wishbone interconnect utilities☆38Updated 8 months ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 5 months ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆11Updated last year
- USB Full Speed PHY☆39Updated 4 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆63Updated 2 months ago
- ☆33Updated 2 months ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆28Updated 3 years ago
- RISC V core implementation using Verilog.☆26Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago