# 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple of good questions. All the Questions will be posted here. If any from the side of users also, if given they will be posted here. Please let me know if there any corrections in the solutions given by me.
☆26Jul 9, 2025Updated last year
Alternatives and similar repositories for 2_Interview_Questions
Users that are interested in 2_Interview_Questions are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆12May 8, 2022Updated 4 years ago
- Schematic, Layout Design & Simulation in 180nm Technology☆23Nov 21, 2020Updated 5 years ago
- Verification of an Asynchronous FIFO using UVM & SVA☆13Jun 26, 2025Updated last year
- Design Verification Engineer interview preparation guide.☆58Jul 20, 2025Updated last year
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆17Dec 8, 2020Updated 5 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Verification IP for APB protocol☆33Sep 9, 2020Updated 6 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 5 years ago
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆29Feb 16, 2026Updated 7 months ago
- This repository contains all the materials related to the basic MOSFET theory, CMOS technology, circuit and layout design, and basic PDK …☆15Dec 15, 2023Updated 2 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- Z-Core - A Lightweight RISC-V Processor (RV32IMZicsr)☆15Sep 6, 2026Updated 2 weeks ago
- Solution for 2022 ICCAD Problem D: Wirelength Driven Detailed Macro Placement☆15Nov 14, 2024Updated last year
- Verilog implementation of Pac-Man made for a class's final project☆19Mar 7, 2012Updated 14 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆52Jul 11, 2025Updated last year
- Monte Carlo Tree Search on Perfect Rectangle Packing Problem Instances☆10Dec 8, 2022Updated 3 years ago
- Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground☆14Feb 24, 2026Updated 6 months ago
- VIP for AXI Protocol☆187May 24, 2022Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆134Feb 22, 2024Updated 2 years ago
- A collection of course materials, notes and assignments for the Masters of Information and Data Sciences program at UC Berkeley☆15Dec 15, 2019Updated 6 years ago
- RISC-V Dual-Issue RV32I Core in SystemVerilog☆28Updated this week
- ☆49Apr 7, 2024Updated 2 years ago
- Scripts for Digital Design flow control.☆17Oct 30, 2025Updated 10 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Feb 13, 2022Updated 4 years ago
- ☆33Jun 5, 2026Updated 3 months ago
- This repository contains course materials, tutorials and exercise for CSE321: Computer Organization course.☆26Dec 17, 2025Updated 9 months ago
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆25Apr 20, 2022Updated 4 years ago
- ☆15May 24, 2025Updated last year
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆14Jun 13, 2021Updated 5 years ago
- ☆14Jun 4, 2024Updated 2 years ago
- Structured UVM Course☆77Jan 4, 2024Updated 2 years ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- The memory model was leveraged from micron.☆32Mar 24, 2018Updated 8 years ago
- Single Cycle CPU using the RV32I Base Instruction set☆24Nov 5, 2025Updated 10 months ago
- This repository contains source code for Universal boot loader This repository contains source code for Universal boot loader for use wit…☆12Aug 19, 2025Updated last year
- SystemVerilog Constraint Layering via Reusable Randomization Policy Classes Examples☆17Mar 8, 2015Updated 11 years ago
- Describes the best coding practices and guidelines☆11Jan 4, 2024Updated 2 years ago
- Submission template for Tiny Tapeout 9 - Verilog HDL Projects☆15Nov 13, 2024Updated last year
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆32Jun 4, 2024Updated 2 years ago