ColsonZhang / VerilogA-Wave-GeneratorLinks
The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your setting.And the setting is done in the python code (main.py), which will facilitate greatly the coding works.
☆54Updated last month
Alternatives and similar repositories for VerilogA-Wave-Generator
Users that are interested in VerilogA-Wave-Generator are comparing it to the libraries listed below
Sorting:
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆189Updated last year
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆249Updated 5 months ago
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆68Updated 7 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆80Updated 2 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆48Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆82Updated 3 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆38Updated 3 years ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆175Updated 3 months ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆36Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆53Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- SDRAM controller with AXI4 interface☆100Updated 6 years ago
- All digital PLL☆28Updated 8 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆101Updated last year
- Delta-Sigma modulator (DSM) for fractional phase locked loop.☆33Updated 4 years ago
- ☆187Updated 4 years ago
- A collection of license features from a varity of EDA vendors☆84Updated 5 months ago
- FFT implement by verilog_测试验证已通过☆60Updated 9 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆160Updated 11 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- An implementation of the CORDIC algorithm in Verilog.☆109Updated 7 years ago
- Pipeline FFT Implementation in Verilog HDL☆159Updated 6 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆200Updated 3 weeks ago
- Verilog RTL Design☆46Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Updated 6 years ago
- ☆74Updated 10 years ago