Alternatives and similar repositories for VerilogA-Wave-Generator:

Users that are interested in VerilogA-Wave-Generator are comparing it to the libraries listed below

• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆56Updated 5 months ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆69Updated 2 years ago
• muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
  This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…
  ☆62Updated last year
• chengquan / IC_FLOW
  ☆14Updated last year
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• muhammadaldacher / Modeling-of-10-bit-Pipeline-ADC-and-10-bit-DAC
  This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …
  ☆23Updated 5 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆52Updated 10 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆93Updated 4 years ago
• muhammadaldacher / Analog-Design-of-Asynchronous-SAR-ADC
  This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…
  ☆141Updated 2 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆85Updated 4 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆64Updated 3 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• kuladeepsaireddy / OpenNoc
  ☆27Updated 5 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆52Updated 8 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆47Updated 10 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆57Updated last year
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆14Updated 3 years ago
• BitOpenFPGA / arl
  lists of most popular repositories for most favoured programming languages (according to StackOverflow)
  ☆77Updated 4 years ago
• fengqzHD / gmIdNeoKit
  Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit
  ☆42Updated 4 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆59Updated 3 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆105Updated 10 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆68Updated 2 years ago
• zlijingtao / Digital-Calibration-of-SAR-ADC
  Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
  ☆51Updated 6 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆77Updated 5 years ago
• xbwpc / EDA_FeatureColle
  A collection of license features from a varity of EDA vendors
  ☆48Updated last year
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆26Updated 5 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆36Updated 5 years ago
• pareddy113 / Design-of-various-multiplier-Array-Booth-Wallace-
  ☆19Updated last year
• filipamator / adpll
  All digital PLL
  ☆27Updated 7 years ago