mit-han-lab / bnn-icestickLinks
Binary Neural Network on IceStick FPGA.
☆51Updated 7 years ago
Alternatives and similar repositories for bnn-icestick
Users that are interested in bnn-icestick are comparing it to the libraries listed below
Sorting:
- Part of paper: Massively Parallel Combinational Binary Neural Networks for Edge Processing☆12Updated 6 years ago
- ☆39Updated 8 years ago
- This is a collection of works on neural networks and neural accelerators.☆41Updated 6 years ago
- ☆14Updated 5 years ago
- Example code and instructions on getting Tensorflow Lite running on a Xilinx Zynq☆49Updated 7 years ago
- ☆37Updated 3 years ago
- Keras implementations of BinaryNet and XNORNet☆55Updated 7 years ago
- An implementation of a BinaryConnect network for cifar10☆11Updated 5 years ago
- Ternary Weights and Activations☆24Updated 7 years ago
- ☆119Updated 7 years ago
- Jupyter notebook examples on image classification with quantized neural networks☆69Updated 5 years ago
- CaffePresso: An Optimized Library for Deep Learning on Embedded Accelerator-based platforms☆87Updated last year
- A regularly updated comparison of CNN architectures in terms of accuracy, operations and model size☆45Updated 6 years ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆144Updated 5 years ago
- ☆46Updated 5 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆17Updated 7 years ago
- NEural Minimizer for pytOrch☆45Updated last year
- Open Source Compiler Framework using ONNX as Frontend and IR☆33Updated 3 years ago
- ☆20Updated 7 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆91Updated 6 years ago
- Codes for Binary Ensemble Neural Network: More Bits per Network or More Networks per Bit?☆31Updated 6 years ago
- ☆62Updated 7 years ago
- Residual Binarized Neural Network☆42Updated 7 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆55Updated 7 years ago
- ☆25Updated 7 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated 2 years ago
- Implementation of Ternary Weight Networks In Caffe☆63Updated 8 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆164Updated 3 years ago
- ☆47Updated 5 years ago
- This is a PyTorch implementation of the Scalpel. Node pruning for five benchmark networks and SIMD-aware weight pruning for LeNet-300-100…☆41Updated 6 years ago