mit-han-lab / bnn-icestick
Binary Neural Network on IceStick FPGA.
☆50Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for bnn-icestick
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆131Updated 4 years ago
- This is a collection of works on neural networks and neural accelerators.☆40Updated 5 years ago
- ☆13Updated 4 years ago
- Reproduction of WAGE in PyTorch.☆41Updated 6 years ago
- Ternary Weights and Activations☆24Updated 6 years ago
- Example code and instructions on getting Tensorflow Lite running on a Xilinx Zynq☆49Updated 6 years ago
- An implementation of a BinaryConnect network for cifar10☆11Updated 5 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆18Updated 6 years ago
- ☆39Updated 7 years ago
- Codes for Binary Ensemble Neural Network: More Bits per Network or More Networks per Bit?☆31Updated 5 years ago
- Keras implementations of BinaryNet and XNORNet☆55Updated 7 years ago
- ☆37Updated 2 years ago
- This is a PyTorch implementation of the Scalpel. Node pruning for five benchmark networks and SIMD-aware weight pruning for LeNet-300-100…☆41Updated 6 years ago
- Caffe to VHDL☆66Updated 4 years ago
- Open Source Compiler Framework using ONNX as Frontend and IR☆29Updated 2 years ago
- ☆53Updated 5 years ago
- A repository containing homework labs for CSE548☆40Updated 7 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 5 years ago
- This repository represents training examples for the CVPR 2018 paper "SYQ:Learning Symmetric Quantization For Efficient Deep Neural Netwo…☆32Updated 5 years ago
- Implementation for the paper "Latent Weights Do Not Exist: Rethinking Binarized Neural Network Optimization"☆73Updated 4 years ago
- NEural Minimizer for pytOrch☆41Updated 4 months ago
- This repository containts the pytorch scripts to train mixed-precision networks for microcontroller deployment, based on the memory contr…☆49Updated 6 months ago
- System Verilog code describing a fully combinational binarized neural network.☆30Updated 6 years ago
- HLS branch of Halide☆77Updated 6 years ago
- FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud☆161Updated 2 years ago
- This code implements NICE papper☆21Updated 6 years ago
- Residual Binarized Neural Network☆44Updated 6 years ago
- Implementation of Ternary Weight Networks In Caffe☆63Updated 7 years ago