Alternatives and similar repositories for zephyr-on-litex-vexriscv:

Users that are interested in zephyr-on-litex-vexriscv are comparing it to the libraries listed below

• ECP5-PCIe / ECP5-Utils
  Utilities for the ECP5 FPGA
  ☆18Updated 3 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 3 weeks ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last week
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago
• polarfire-soc / polarfire-soc-linux-examples
  ☆13Updated 2 months ago
• olofk / simple_spi
  SPI core
  ☆15Updated 5 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆41Updated 2 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆25Updated 5 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆13Updated 4 years ago
• britovski / adder
  Adder in VHDL to test the digital flow using ghdl and GTKwave (front-end) and openlane (back-end). Translated from the original https://g…
  ☆11Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆24Updated last year
• YosysHQ / sby-gui
  GUI for SymbiYosys
  ☆13Updated 9 months ago
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• YosysHQ / prjtrellis-db
  Project Trellis database
  ☆13Updated last year
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆27Updated 2 years ago
• litex-hub / litespi
  Small footprint and configurable SPI core
  ☆40Updated last week
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 3 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• QuickLogic-Corp / quicklogic-fpga-toolchain
  Open Source FPGA toolchain and documentation for QuickLogic devices and eFPGA IP
  ☆36Updated 3 years ago
• varunnagpaal / Analog-Design-Modelling
  Analog Hardware Hands on Design Labs and Modelling using SPICE Tools (NI Multisim, LTSpice)
  ☆23Updated 6 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 8 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆24Updated 5 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• FPGAwars / Collection-stdio
  Icestudio collection for standard Input-Output in different devices
  ☆14Updated 6 months ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆32Updated 3 years ago
• tongchen126 / fpga_pcie_ethernet
  ☆15Updated 2 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year