Alternatives and similar repositories for zephyr-on-litex-vexriscv

Users that are interested in zephyr-on-litex-vexriscv are comparing it to the libraries listed below

• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated last month
• ECP5-PCIe / ECP5-Utils
  Utilities for the ECP5 FPGA
  ☆18Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated 3 weeks ago
• olofk / simple_spi
  SPI core
  ☆15Updated 5 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆13Updated 4 years ago
• YosysHQ / sby-gui
  GUI for SymbiYosys
  ☆15Updated last year
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated last week
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• cambridgehackers / fpgajtag
  A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
  ☆35Updated 2 years ago
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated last week
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• ulx3s / ulx3s-toolchain
  ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts
  ☆39Updated 4 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆21Updated 7 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• mithro / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆17Updated 5 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆42Updated 2 months ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated last year
• enjoy-digital / litex_vexriscv_smp_test
  VexRiscv-SMP integration test with LiteX.
  ☆25Updated 4 years ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆19Updated 3 weeks ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆33Updated 3 years ago
• bunnie / netv2-soc
  NeTV2 SoC based on LiteX
  ☆16Updated 6 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago