litex-hub / zephyr-on-litex-vexriscv
☆12Updated 7 months ago
Alternatives and similar repositories for zephyr-on-litex-vexriscv:
Users that are interested in zephyr-on-litex-vexriscv are comparing it to the libraries listed below
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 3 weeks ago
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- USB Full-Speed core written in migen/LiteX☆17Updated 5 years ago
- SPI core☆15Updated 5 years ago
- HDMI Expansion Modules compatible with the Pmod standard☆11Updated 7 years ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated last month
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- Xilinx Virtual Cable Daemon☆19Updated 5 years ago
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆21Updated 9 months ago
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆13Updated 4 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 4 months ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 3 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 9 months ago
- This repository contains sample code integrating Renode with Verilator☆19Updated last week
- FLIX-V: FPGA, Linux and RISC-V☆41Updated last year
- Open Source AES☆31Updated last year
- Simple RS232 UART☆12Updated 9 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Cross compile FPGA tools☆22Updated 4 years ago
- Full Speed USB DFU interface for FPGA and ASIC designs☆17Updated last year
- Yosys Plugins☆21Updated 5 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- RISC-V System on Chip Builder☆12Updated 4 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 2 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- DyRACT Open Source Repository☆16Updated 8 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year