Alternatives and similar repositories for SDSoC-platforms

Users that are interested in SDSoC-platforms are comparing it to the libraries listed below

• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆22Updated 6 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• warclab / idea
  iDEA FPGA Soft Processor
  ☆16Updated 9 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated last month
• Digilent / Petalinux-Zybo
  ☆27Updated 7 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• Domipheus / ArtyS7-RPU-SoC
  Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
  ☆39Updated 5 years ago
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆45Updated 3 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆71Updated 3 years ago
• ObKo / USBCore
  USB Full-Speed/Hi-Speed Device Controller core for FPGA
  ☆33Updated 5 years ago
• librecores / docker-images
  CI Docker Images
  ☆19Updated 5 years ago
• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 4 years ago
• bgottschall / reloc
  Designing Relocatable FPGA Partitions with Vivado Design Suite
  ☆10Updated 7 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆20Updated 6 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆42Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• olofk / observer
  ☆43Updated 5 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆45Updated 10 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated last year
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 6 years ago
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 4 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆72Updated 8 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆92Updated 7 years ago
• pliu6 / vhd2vl
  vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
  ☆26Updated 10 years ago
• mnentwig / busbridge3
  Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency
  ☆20Updated 6 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago