Alternatives and similar repositories for SDSoC-platforms:

Users that are interested in SDSoC-platforms are comparing it to the libraries listed below

• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆21Updated 5 years ago
• bgottschall / reloc
  Designing Relocatable FPGA Partitions with Vivado Design Suite
  ☆10Updated 7 years ago
• warclab / idea
  iDEA FPGA Soft Processor
  ☆16Updated 8 years ago
• drom / atom-hide
  Atom Hardware IDE
  ☆13Updated 3 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆44Updated 9 years ago
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• rbarzic / arty-cm0-designstart
  A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
  ☆12Updated 6 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆17Updated 3 weeks ago
• HarmonInstruments / verilog
  ☆20Updated 2 years ago
• UGent-HES / tlut_flow
  TLUT tool flow for parameterised configurations for FPGAs
  ☆16Updated 8 months ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 9 months ago
• umarcor / hwstudio
  GUI editor for hardware description designs
  ☆28Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last month
• antmicro / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆20Updated this week
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated last week
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆34Updated 7 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 5 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆19Updated 8 months ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆18Updated 5 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 7 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 5 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• jkorinth / chisel-packaging
  IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.
  ☆10Updated 6 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago