Alternatives and similar repositories for gem5-noc

Users that are interested in gem5-noc are comparing it to the libraries listed below

• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 3 months ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆68Updated last year
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆32Updated 5 years ago
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆29Updated 3 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• Jpz-sdju / trinity
  ☆27Updated last month
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆25Updated 2 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆43Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆52Updated 3 years ago
• OpenXiangShan / GEM5
  ☆101Updated this week
• yonseicasl / NPUsim
  NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators
  ☆42Updated 8 months ago
• OSCPU / ysyxSoC
  ☆86Updated this week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆67Updated last year
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• OSCPU / yosys-sta
  ☆82Updated 5 months ago
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 4 years ago
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆21Updated 7 years ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆23Updated 9 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆63Updated 9 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆68Updated last week
• pulp-platform / fpu
  ☆53Updated 6 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆32Updated 7 months ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆32Updated 3 months ago
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆11Updated 6 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆64Updated 2 years ago
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆17Updated 5 months ago