NoC simulation using gem5 (a simple tul)
☆16Mar 23, 2024Updated 2 years ago
Alternatives and similar repositories for gem5-noc
Users that are interested in gem5-noc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆19Aug 27, 2025Updated 11 months ago
- SystemC training aimed at TLM.☆35Jul 31, 2020Updated 6 years ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 12 years ago
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆13Oct 14, 2021Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Cost Model☆20Apr 11, 2025Updated last year
- A high-performance C++20 cache simulator with power/area modeling, MESI coherence, prefetching, and multi-level hierarchy support for arc…☆16Feb 10, 2026Updated 6 months ago
- gem5 repository to study chiplet-based systems☆91Apr 18, 2019Updated 7 years ago
- Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…☆26Mar 29, 2025Updated last year
- ☆16May 1, 2026Updated 3 months ago
- A list of our chiplet simulaters☆50Jun 22, 2025Updated last year
- some knowleage about SystemC/TLM etc.☆28Mar 6, 2026Updated 5 months ago
- ☆17Jul 10, 2026Updated last month
- Criticality-aware Framework for Modeling Computer Performance☆34Dec 15, 2024Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆24Nov 27, 2025Updated 8 months ago
- The best rtl_uart in github! This is a UART design based on AXI Stream/Ready Vallid protocol. Support parameterized data bit width, clock…☆11May 8, 2025Updated last year
- ☆10Oct 8, 2021Updated 4 years ago
- data preprocessing scripts for gem5 output☆19May 23, 2025Updated last year
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆16Jan 4, 2023Updated 3 years ago
- This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, Syst…☆17Jun 26, 2024Updated 2 years ago
- ☆14Oct 8, 2024Updated last year
- Library for modelling performance costs of different Neural Network workloads on NPU devices☆36Jul 23, 2026Updated 3 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 关于移植模型至gemmini的文档☆34May 4, 2022Updated 4 years ago
- Sampled simulation of multi-threaded applications using LoopPoint methodology☆25Feb 21, 2026Updated 5 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆45Aug 10, 2022Updated 4 years ago
- ☆28Feb 28, 2026Updated 5 months ago
- 哈尔滨工业大学（深圳）2021年球季学期深度学习体系结构实验☆17Oct 1, 2022Updated 3 years ago
- A parallel and distributed simulator for thousand-core chips☆27Apr 10, 2018Updated 8 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- RocketChip RoCC Accelerator template (Risc-V, Chisel )(加速器开发项目框架)☆15Sep 5, 2019Updated 6 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆34May 17, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- L1 Data, L1 Instruction and L2 Unified Cache Design☆16May 26, 2026Updated 2 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆154Jul 22, 2025Updated last year
- CQU Dual Issue Machine☆42Jun 23, 2024Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆57Jun 30, 2017Updated 9 years ago
- ☆13May 21, 2020Updated 6 years ago
- Network on Chip Simulator☆333Jun 9, 2026Updated 2 months ago
- ☆15Feb 2, 2026Updated 6 months ago