amromanov / vmodel
Vmodel toolbox repository
☆14Updated 8 years ago
Alternatives and similar repositories for vmodel:
Users that are interested in vmodel are comparing it to the libraries listed below
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆28Updated 6 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆16Updated 9 months ago
- Advanced Debug Interface☆13Updated 3 weeks ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆15Updated 5 years ago
- Universal Advanced JTAG Debug Interface☆17Updated 9 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- ☆36Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Announcements related to Verilator☆39Updated 4 years ago
- Automatic SystemVerilog linting in github actions with the help of Verible☆33Updated 3 months ago
- ☆63Updated 6 years ago
- Open Processor Architecture☆26Updated 8 years ago
- ☆22Updated last year
- SoCRocket - Core Repository☆34Updated 7 years ago
- Extensible FPGA control platform☆57Updated last year
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- SCARV: a side-channel hardened RISC-V platform☆24Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆21Updated last month
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 7 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- Hardware Verification library for C++, SystemC and SystemVerilog☆29Updated 12 years ago