简洁的测试平台日志，波形(FSDB/VCD)，根因分析MCP Server. A Simple and Universal MCP Server to Debug Testbench Simulation Failures Via Log Parsing And Waveform Analysis (FSDB/VCD)
☆56Jul 21, 2026Updated this week
Alternatives and similar repositories for TraceWeave
Users that are interested in TraceWeave are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆58May 22, 2026Updated 2 months ago
- Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP sp…☆18Jul 14, 2026Updated last week
- 面向 AI 编程 Agent 的开源形式验证技能库，聚焦 FPV、SVA、证明优化、TCL 脚本与可扩展的形式验证工作流。Open-source formal verification skills for AI coding agents, focused on FPV,…☆21Updated this week
- ☆20May 22, 2026Updated 2 months ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Parse FSDB waveform files☆23Apr 13, 2026Updated 3 months ago
- SystemVerilog Design Patterns☆26Mar 11, 2015Updated 11 years ago
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- Generative Benchmark for LLM-Aided Hardware Design☆29Jun 4, 2025Updated last year
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 5 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 3 weeks ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- EpicSim Project☆71Mar 1, 2021Updated 5 years ago
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆17Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆25Mar 25, 2025Updated last year
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆50Mar 3, 2024Updated 2 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆40Aug 26, 2016Updated 9 years ago
- ☆174Mar 10, 2025Updated last year
- A header only C++11 library for functional coverage☆35Oct 5, 2022Updated 3 years ago
- ☆23Mar 19, 2026Updated 4 months ago
- Open-Source Framework for Co-Emulation☆13Feb 12, 2021Updated 5 years ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆36Jul 2, 2026Updated 2 weeks ago
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- AI-Powered Hardware Design & Verification Copilot - Plugin for your CLI☆22Jul 12, 2026Updated last week
- pyslang-mcp is a read-only Model Context Protocol server for compiler-backed Verilog and SystemVerilog analysis. It uses pyslang to parse…☆19Jun 14, 2026Updated last month
- System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers☆80Mar 6, 2019Updated 7 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 7 years ago
- SystemC Configuration, Control and Inspection (CCI)☆22Jul 7, 2026Updated 2 weeks ago
- FPU Generator☆20Updated this week
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A Claude Code plugin for process management from requirement sorting to delivery☆21Jun 4, 2026Updated last month
- 正点原子开拓者&新起点FPGA开发板例程☆15Nov 29, 2019Updated 6 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- Generic AXI interconnect fabric☆13Jul 17, 2014Updated 12 years ago
- host memory buffer feature based on OpenFabrics NVMe Windows driver☆15Dec 8, 2017Updated 8 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆19Dec 23, 2025Updated 6 months ago