avidan-efody / wave_searcher
Implementation of post-process coverage, and batch waveform search
☆15Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for wave_searcher
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆25Updated 3 weeks ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated last week
- Useful UVM extensions☆20Updated 4 months ago
- CORE-V MCU UVM Environment and Test Bench☆17Updated 4 months ago
- YosysHQ SVA AXI Properties☆32Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆29Updated 3 years ago
- DUTH RISC-V Microprocessor☆19Updated last week
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- Constrained RAndom Verification Enviroment (CRAVE)☆16Updated 11 months ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆34Updated 5 months ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆15Updated 6 months ago
- Simple template-based UVM code generator☆20Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- SystemVerilog Linter based on pyslang☆23Updated 8 months ago
- Mirror of the Universal Verification Methodology from sourceforge☆32Updated 9 years ago
- APB UVC ported to Verilator☆11Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆23Updated 5 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- Connecting SystemC with SystemVerilog☆36Updated 12 years ago
- SoC Based on ARM Cortex-M3☆25Updated 6 months ago
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆34Updated 8 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Python Tool for UVM Testbench Generation☆48Updated 6 months ago
- SystemVerilog Logger☆16Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- Generate UVM testbench framework template files with Python 3☆21Updated 4 years ago