Implementation of post-process coverage, and batch waveform search
☆18Aug 29, 2021Updated 5 years ago
Alternatives and similar repositories for wave_searcher
Users that are interested in wave_searcher are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆70Aug 18, 2021Updated 5 years ago
- CORE-V MCU UVM Environment and Test Bench☆29Jul 19, 2024Updated 2 years ago
- SystemVerilog Logger☆19Apr 6, 2026Updated 4 months ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- UVM VIP architecture generator☆21Aug 24, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 6 years ago
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 10 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Updated this week
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 8 years ago
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 9 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 6 years ago
- ☆15Jun 27, 2024Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- SoC based on RISC V ISA☆10Apr 22, 2022Updated 4 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆41Aug 26, 2016Updated 10 years ago
- The source code of blog☆14Dec 12, 2021Updated 4 years ago
- Libraries and tools for KiCAD EDA suite☆17Dec 5, 2021Updated 4 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- ☆37Mar 3, 2016Updated 10 years ago
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 5 years ago
- DUTH RISC-V Microprocessor☆26Apr 5, 2026Updated 4 months ago
- SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)☆72Jan 14, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD☆37Apr 20, 2021Updated 5 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆39Updated this week
- Read only mirror of SVN ChibiOS repository. Official forum http://forum.chibios.org Bugtracker http://sourceforge.net/projects/chibios☆18Sep 2, 2019Updated 7 years ago
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated 7 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- Verification IP for AMBA APB Protocol☆35Nov 7, 2023Updated 2 years ago
- AXI PSRAM Controller IP for use with Digilent Nexys 4☆11Jun 19, 2026Updated 2 months ago
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 10 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- SystemVerilog Constraint Layering via Reusable Randomization Policy Classes Examples☆17Mar 8, 2015Updated 11 years ago
- Multi-instance MCTP daemon application.☆10Oct 7, 2024Updated last year
- ☆11Nov 5, 2019Updated 6 years ago
- ☆11May 30, 2024Updated 2 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆58Jan 21, 2017Updated 9 years ago
- YAMM package repository☆34Mar 20, 2023Updated 3 years ago
- Simple template-based UVM code generator☆31Apr 15, 2026Updated 4 months ago