I2C master/slave Core
☆15Jul 17, 2014Updated 11 years ago
Alternatives and similar repositories for i2c_master_slave_core
Users that are interested in i2c_master_slave_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- I2C Slave☆14Jul 17, 2014Updated 11 years ago
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- I2C Master and Slave☆41Jul 15, 2015Updated 10 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Jul 14, 2024Updated last year
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆28Feb 24, 2026Updated 4 months ago
- Design and UVM Verification of an ALU☆13Jun 14, 2024Updated 2 years ago
- ☆19Jun 30, 2015Updated 11 years ago
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- ☆13Nov 18, 2025Updated 7 months ago
- RV64IMAC modelling using System Verilog HDL☆25Aug 10, 2024Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- A complete UVM verification testbench for FIFO☆14Mar 21, 2016Updated 10 years ago
- Add-on project for Chaste for modelling microvessels.☆10Aug 6, 2024Updated last year
- ☆11Nov 22, 2016Updated 9 years ago
- Verilog I2C Slave☆26Aug 11, 2014Updated 11 years ago
- A proposed method for automated diagnosis of various diseases based on heart rate variability (HRV) analysis and machine learning. HRV an…☆11Apr 9, 2020Updated 6 years ago
- Learn how to develop a plugin for PlotJuggler, by example.☆19Aug 15, 2023Updated 2 years ago
- this is a cnn_net to achieve the goal of using ppg to predict blood pressure☆10Jun 16, 2018Updated 8 years ago
- A simple Python implementation of Pan-Tompkins algorithm for QRS complex detection☆12Jul 21, 2016Updated 9 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆31Feb 22, 2024Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated last year
- Bare metal RISC-V assembly examples for Spike (no pk)☆19Oct 14, 2023Updated 2 years ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 7 years ago
- Nios II Vscode Extension☆10Sep 17, 2020Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆39Jun 2, 2021Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆34Jun 27, 2024Updated 2 years ago
- This is an unofficial ITMO beamer template made by me. Please, feel free to use it and contribute.☆15Oct 10, 2023Updated 2 years ago
- This repository is an artifact for the paper "CNNs for Heart Rate Estimation and Human Activity Recognition in Wrist Worn Sensing Applica…☆15Jan 6, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Code Developed for my Masters Thesis titled: A real-time independent and inexpensive PPG signal quality classification tool for vital sig…☆13Jun 21, 2020Updated 6 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 4 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆29Jul 27, 2018Updated 7 years ago
- M.2 PCIe Artix 7 FPGA Accelerator Card☆31Mar 17, 2025Updated last year
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- A verilog based 5-stage pipelined RISC-V Processor code.☆40Mar 25, 2020Updated 6 years ago
- Building Linux System Software with Xilinx Vitis 2022.1 and Buildroot for Zynq 7000 / ZynqMP platforms.☆21Mar 26, 2024Updated 2 years ago