I2C master/slave Core
☆15Jul 17, 2014Updated 11 years ago
Alternatives and similar repositories for i2c_master_slave_core
Users that are interested in i2c_master_slave_core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- I2C Slave☆14Jul 17, 2014Updated 11 years ago
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- I2C Master and Slave☆38Jul 15, 2015Updated 10 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Automated UVM testbench generator from Verilog RTL with optional LLM integration for advanced logic creation.☆19Feb 24, 2026Updated last month
- Open source tools for IC design☆13Dec 12, 2024Updated last year
- ☆19Jun 30, 2015Updated 10 years ago
- Design and UVM Verification of an ALU☆13Jun 14, 2024Updated last year
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- ☆12Nov 18, 2025Updated 5 months ago
- RV64IMAC modelling using System Verilog HDL☆24Aug 10, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- General Purpose IO with APB4 interface☆16May 10, 2024Updated last year
- A complete UVM verification testbench for FIFO☆14Mar 21, 2016Updated 10 years ago
- Annotate signal, timeseries, waveforms...☆10Aug 3, 2020Updated 5 years ago
- ☆10Nov 22, 2016Updated 9 years ago
- Verilog I2C Slave☆25Aug 11, 2014Updated 11 years ago
- A proposed method for automated diagnosis of various diseases based on heart rate variability (HRV) analysis and machine learning. HRV an…☆11Apr 9, 2020Updated 6 years ago
- Learn how to develop a plugin for PlotJuggler, by example.☆17Aug 15, 2023Updated 2 years ago
- Mirror of the Universal Verification Methodology from sourceforge☆37Jan 21, 2015Updated 11 years ago
- this is a cnn_net to achieve the goal of using ppg to predict blood pressure☆10Jun 16, 2018Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 基于脉搏波的亚健康手环☆12Jun 21, 2022Updated 3 years ago
- ☆25Feb 22, 2024Updated 2 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆27Sep 8, 2024Updated last year
- Репозиторий факультатива по функциональной верификации НИУ МИЭТ☆16Aug 24, 2024Updated last year
- Bare metal RISC-V assembly examples for Spike (no pk)☆19Oct 14, 2023Updated 2 years ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- I2C slave Verilog Design and TestBench☆27May 9, 2019Updated 6 years ago
- Nios II Vscode Extension☆10Sep 17, 2020Updated 5 years ago
- Design and UVM-TB of RISC -V Microprocessor☆36Jun 27, 2024Updated last year
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- DEPRECATED. Please use Chipyard (https://github.com/ucb-bar/chipyard) to build BOOM☆37Oct 23, 2019Updated 6 years ago
- This repository is an artifact for the paper "CNNs for Heart Rate Estimation and Human Activity Recognition in Wrist Worn Sensing Applica…☆15Jan 6, 2021Updated 5 years ago
- M.2 PCIe Artix 7 FPGA Accelerator Card☆22Mar 17, 2025Updated last year
- Code Developed for my Masters Thesis titled: A real-time independent and inexpensive PPG signal quality classification tool for vital sig…☆13Jun 21, 2020Updated 5 years ago
- verilog filetype plugin to enable emacs verilog-mode autos☆17Apr 24, 2022Updated 3 years ago
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆29Jul 27, 2018Updated 7 years ago
- Systolic Blood Pressure level based on PPG signal's parameteres☆12Jun 4, 2018Updated 7 years ago