salehjg / DeepPoint-V2-FPGALinks
The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs
☆15Updated 2 years ago
Alternatives and similar repositories for DeepPoint-V2-FPGA
Users that are interested in DeepPoint-V2-FPGA are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆124Updated 2 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆75Updated 5 months ago
- ☆113Updated 4 years ago
- An FPGA Accelerator for Transformer Inference☆85Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- IC implementation of Systolic Array for TPU☆260Updated 8 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆216Updated 2 years ago
- AMD University Program HLS tutorial☆99Updated 8 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆147Updated this week
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 5 years ago
- ☆10Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- Deep Learning Accelerator (Convolution Neural Networks)☆188Updated 7 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆124Updated 5 months ago
- eyeriss-chisel3☆41Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆40Updated 11 months ago
- ☆33Updated 10 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆179Updated last year
- AutoSA: Polyhedral-Based Systolic Array Compiler☆221Updated 2 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆102Updated 4 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated last year
- Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximat…☆15Updated 2 years ago
- some knowleage about SystemC/TLM etc.☆25Updated 2 years ago
- ☆41Updated 4 years ago
- ☆44Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆129Updated 4 months ago
- Vitis HLS Library for FINN☆202Updated this week