jiacaiyuan / i2c_slave

Related projects ⓘ

Alternatives and complementary repositories for i2c_slave

• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆55Updated 3 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆55Updated 9 months ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆45Updated 3 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆17Updated last year
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆29Updated 3 years ago
• makararasi / UVM_AXI4-Stream
  ☆12Updated 2 years ago
• PXVI / ip_amba_apb_ms_rtl_v
  The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )
  ☆12Updated 2 years ago
• huhuikevin / i2c_slave
  fpga i2c slave verilog hdl rtl
  ☆11Updated 8 years ago
• shubhi704 / APB-Protocol
  ☆36Updated 3 years ago
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆31Updated 4 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆49Updated 2 years ago
• rooinasuit / AXI_to_SPI
  Designing means to communicate as an SPI master, being a part of AXI interface
  ☆16Updated last year
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆46Updated 8 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆33Updated 9 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• kkudrolli / USB-Host
  Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …
  ☆13Updated 9 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆29Updated 2 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆21Updated last year
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆32Updated 8 years ago
• pendkeomkar / SPI
  Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…
  ☆17Updated 6 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆27Updated 4 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆37Updated 4 years ago
• wudayemen / gen_apb_file
  ☆62Updated 3 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆50Updated 10 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆29Updated 9 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆34Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆42Updated 11 months ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆41Updated 6 months ago
• freecores / apbi2c
  APB to I2C
  ☆40Updated 10 years ago
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆27Updated 6 months ago