Alternatives and similar repositories for onikiri2:

Users that are interested in onikiri2 are comparing it to the libraries listed below

• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆101Updated 2 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 3 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 6 months ago
• RIKEN-RCCS / riken_simulator
  This is the git repository for RIKEN simulator designed to simulate the binary code for Fujitsu A64FX.
  ☆34Updated 4 years ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆52Updated 4 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆44Updated 3 years ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 4 years ago
• synthesijer / synthesijer
  ☆52Updated 5 months ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆102Updated 2 months ago
• i4kimura / chisel-minicpu
  ☆14Updated 5 years ago
• Hara-Laboratory / subrisc
  SubRISC: Simple Instruction-Set Computer for IoT edge devices
  ☆16Updated 6 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆36Updated last month
• tmatsuya / wiki
  ☆36Updated 7 years ago
• moizumi99 / m99_riscv_emulator
  Simple RISC-V emulator
  ☆16Updated 4 years ago
• sakura-internet / nvme-pcie-to-fabrics-proxy
  (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…
  ☆20Updated last year
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆148Updated 2 months ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• RuSys / Verugent
  Verilog generation tool written in Rust
  ☆57Updated last year
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆28Updated 5 months ago
• VLSI-JP / VLSI-JP.github.io
  ☆19Updated last month
• ryuz / jelly
  Original FPGA platform
  ☆54Updated last week
• chadyuu / riscv-chisel-book
  ☆220Updated last year
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated 8 months ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆19Updated 3 months ago
• aquaxis / synverll
  ☆14Updated 8 years ago
• NextMicon / NextMiconIDE
  🛠️ Graphical IDE for NextMicon
  ☆27Updated 11 months ago
• ep2k / epGB
  Game Boy / Game Boy Color emulator running on an FPGA
  ☆16Updated 6 months ago
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆52Updated 8 years ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago