Alternatives and similar repositories for Gaia

Users that are interested in Gaia are comparing it to the libraries listed below

• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆17Updated 4 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆39Updated 8 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 5 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆27Updated last year
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆42Updated 6 years ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆37Updated 11 years ago
• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆14Updated 8 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆23Updated 5 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆18Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆23Updated 6 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated 2 weeks ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆33Updated 5 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆26Updated last year
• letitbe0201 / AXI-DMA-master-verification
  ☆27Updated 4 years ago
• svunit / svmock
  A mock framework for use with SVUnit
  ☆19Updated 2 years ago
• taichi-ishitani / tvip-common
  ☆15Updated last year
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 7 years ago
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆37Updated last year
• pulp-platform / axi2apb
  ☆22Updated 5 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆38Updated 3 years ago
• troyguo / dvcon_download
  Download proccedings from DVCon
  ☆22Updated 4 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• hjking / uvm_gen
  UVM Generator
  ☆50Updated last year
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆57Updated 9 years ago
• pulp-platform / uvm-components
  Contains commonly used UVM components (agents, environments and tests).
  ☆32Updated 7 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆38Updated 5 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆32Updated last year
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆27Updated 9 years ago