taichi-ishitani / rggen

Related projects ⓘ

Alternatives and complementary repositories for rggen

• antmicro / cocotb-verilator-build
  ☆26Updated last year
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 6 years ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated this week
• pulp-platform / axi_spi_slave
  ☆23Updated 3 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆53Updated 4 months ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆26Updated 9 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆64Updated 2 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆47Updated 2 months ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆57Updated 5 months ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated last month
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆25Updated 3 weeks ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆34Updated 8 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆15Updated 6 months ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆19Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆48Updated 6 months ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆36Updated 12 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆16Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆34Updated this week
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆50Updated 4 years ago
• Lampro-Mellon / Chisel-Training
  ☆21Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆32Updated 3 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated last month
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆15Updated 4 years ago
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆24Updated 8 years ago