taichi-ishitani / rggen
This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
☆17Updated 5 years ago
Alternatives and similar repositories for rggen:
Users that are interested in rggen are comparing it to the libraries listed below
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Updated 3 months ago
- Import and export IP-XACT XML register models☆34Updated 6 months ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆60Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 7 months ago
- ☆26Updated last year
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Generate address space documentation HTML from compiled SystemRDL input☆50Updated 7 months ago
- UART models for cocotb☆27Updated 2 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Updated last year
- A tool for merging the MyHDL workflow with Vivado☆20Updated 4 years ago
- Python/Simulator integration using procedure calls☆9Updated 5 years ago
- SystemVerilog Logger☆17Updated 2 years ago
- ☆31Updated last year
- Running Python code in SystemVerilog☆68Updated 8 months ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 5 months ago
- ☆20Updated 5 years ago
- Platform Level Interrupt Controller☆39Updated 11 months ago
- hardware library for hwt (= ipcore repo)☆37Updated 4 months ago
- IP-XACT XML binding library☆15Updated 8 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- Python interface for cross-calling with HDL☆31Updated last month
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- An example Python-based MDV testbench for apbi2c core☆30Updated 8 months ago
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Doxygen with verilog support☆37Updated 6 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- ☆33Updated last year