This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
☆18Aug 1, 2019Updated 6 years ago
Alternatives and similar repositories for rggen
Users that are interested in rggen are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 9 years ago
- Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)☆35Jul 9, 2021Updated 4 years ago
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42May 24, 2020Updated 5 years ago
- HOG + SVM on FPGA☆28Dec 16, 2020Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆12May 31, 2016Updated 9 years ago
- Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…☆108Jan 29, 2022Updated 4 years ago
- Polyphony is Python based High-Level Synthesis compiler.☆110Apr 5, 2026Updated 2 weeks ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆12Jan 15, 2017Updated 9 years ago
- ☆29Jun 13, 2021Updated 4 years ago
- ☆15May 10, 2019Updated 6 years ago
- Python like C++ Argument parser☆18Jun 16, 2019Updated 6 years ago
- ☆24Feb 15, 2013Updated 13 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Half-precision floating point for NumPy☆13Nov 10, 2010Updated 15 years ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 12 years ago
- ☆16Apr 17, 2022Updated 4 years ago
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆12Jun 3, 2025Updated 10 months ago
- Filelist generator☆20Mar 31, 2026Updated 2 weeks ago
- General Purpose I/O agent written in UVM☆18Jun 29, 2017Updated 8 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 4 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Mar 16, 2018Updated 8 years ago
- Example Projects for the Microsemi SmartFusion 2☆11Dec 10, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Constrained RAndom Verification Enviroment (CRAVE)☆19Nov 23, 2023Updated 2 years ago
- SystemRDL 2.0 language compiler front-end☆275Apr 10, 2026Updated last week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆15Mar 31, 2026Updated 2 weeks ago
- An experimental package manager and development tool for Hardware Description Languages (HDL).☆14Apr 10, 2022Updated 4 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- Userspace DMA library for Zynq-based SoCs☆16Jan 22, 2019Updated 7 years ago
- ☆15Jul 3, 2024Updated last year
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Connecting SystemC with SystemVerilog☆42Mar 25, 2012Updated 14 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆20Jun 4, 2020Updated 5 years ago
- A collection of Opal Kelly provided design resources☆17Nov 7, 2025Updated 5 months ago
- UVM Generator☆49May 9, 2024Updated last year
- Network on Chip Implementation written in SytemVerilog☆201Aug 27, 2022Updated 3 years ago
- A python replacement for the Tcl interface to quartus☆13Dec 3, 2016Updated 9 years ago
- IP-core package generator for AXI4/Avalon☆23Nov 25, 2018Updated 7 years ago
- a playground for xilinx zynq fpga experiments☆50Nov 19, 2018Updated 7 years ago