openrisc / or1200

Related projects ⓘ

Alternatives and complementary repositories for or1200

• RoaLogic / RV12
  RISC-V CPU Core
  ☆289Updated 5 months ago
• openrisc / mor1kx
  mor1kx - an OpenRISC 1000 processor IP core
  ☆498Updated last month
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆259Updated 4 years ago
• onchipuis / mriscv
  A 32-bit Microcontroller featuring a RISC-V core
  ☆148Updated 6 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆116Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆250Updated this week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆389Updated last month
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆397Updated 5 years ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆263Updated 3 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆215Updated last year
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆79Updated 5 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆199Updated 4 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆201Updated 3 years ago
• sifive / sifive-blocks
  Common RTL blocks used in SiFive's projects
  ☆179Updated 2 years ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆168Updated 4 months ago
• subbdue / systemverilog.io
  Code used in
  ☆174Updated 7 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆123Updated 5 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆222Updated last month
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆327Updated 7 years ago
• sergeykhbr / riscv_vhdl
  Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
  ☆626Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆266Updated last year
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆194Updated last month
• openrisc / orpsoc-cores
  Core description files for FuseSoC
  ☆123Updated 4 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆438Updated last month
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆310Updated 2 years ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆491Updated 10 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆124Updated 4 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆127Updated 2 months ago