OpenRISC 1200 implementation
☆180Nov 11, 2015Updated 10 years ago
Alternatives and similar repositories for or1200
Users that are interested in or1200 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- mor1kx - an OpenRISC 1000 processor IP core☆583Aug 21, 2025Updated 9 months ago
- Core description files for FuseSoC☆125Jun 26, 2020Updated 5 years ago
- OpenRISC Tutorials☆50Apr 3, 2026Updated last month
- The OpenRISC 1000 architectural simulator☆78Apr 27, 2025Updated last year
- GCC port for OpenRISC 1000☆26Mar 29, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Linux kernel source tree☆34Feb 11, 2026Updated 3 months ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Jan 15, 2016Updated 10 years ago
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆35Feb 18, 2022Updated 4 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆73Mar 31, 2018Updated 8 years ago
- OpenRISC Conference Website☆15Aug 15, 2024Updated last year
- Source for openrisc.io☆13Jun 29, 2025Updated 10 months ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆37Dec 24, 2020Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆51Aug 24, 2024Updated last year
- The source code that empowers OpenROAD Cloud☆13Jun 29, 2020Updated 5 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 13 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆378Jul 12, 2017Updated 8 years ago
- newlib OpenRISC development☆27Mar 30, 2025Updated last year
- ☆17Nov 25, 2017Updated 8 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 3 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆10Apr 27, 2026Updated 3 weeks ago
- An open-source microcontroller system based on RISC-V☆1,036Feb 6, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15☆22Dec 22, 2020Updated 5 years ago
- VeeR EL2 Core☆338Updated this week
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21May 24, 2023Updated 3 years ago
- vhdl related contents☆11Apr 27, 2020Updated 6 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆87Dec 23, 2018Updated 7 years ago
- VeeR EH1 core☆945May 29, 2023Updated 2 years ago
- download from opencores.org☆16May 4, 2018Updated 8 years ago
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated last month
- The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.☆82Mar 11, 2012Updated 14 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆21Apr 9, 2013Updated 13 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Dec 3, 2025Updated 5 months ago
- an sata controller using smallest resource.☆17Feb 5, 2014Updated 12 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,149Jun 27, 2024Updated last year
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 6 years ago
- Programmable multichannel ADPCM decoder for FPGA☆26Dec 28, 2020Updated 5 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆552Nov 26, 2024Updated last year