OpenRISC 1200 implementation
☆184Nov 11, 2015Updated 10 years ago
Alternatives and similar repositories for or1200
Users that are interested in or1200 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- mor1kx - an OpenRISC 1000 processor IP core☆593Jun 6, 2026Updated 4 months ago
- OpenRISC 1000 port for sourceware.org's src tree (binutils, gdb, newlib, etc.)☆19Mar 12, 2016Updated 10 years ago
- Core description files for FuseSoC☆125Jun 26, 2020Updated 6 years ago
- OpenRISC Tutorials☆51Jul 18, 2026Updated 3 months ago
- GCC port for OpenRISC 1000☆26Mar 29, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- OpenRISC processor IP core based on Tomasulo algorithm☆37Feb 18, 2022Updated 4 years ago
- The OpenRISC 1000 architectural simulator☆80Apr 27, 2025Updated last year
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Linux kernel source tree☆36Aug 29, 2026Updated 2 months ago
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- OpenRISC Conference Website☆16Aug 15, 2024Updated 2 years ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Jan 15, 2016Updated 10 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆77Mar 31, 2018Updated 8 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 14 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- OpenSPARC-based SoC☆78Jul 17, 2014Updated 12 years ago
- Development and verification environment for the mor1kx core☆12Dec 29, 2014Updated 11 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆39Dec 24, 2020Updated 5 years ago
- VeeR EH1 core☆971Jul 16, 2026Updated 3 months ago
- Car Diagnostics Software compatible with ELM327 OBD usb device☆11May 10, 2025Updated last year
- An open-source microcontroller system based on RISC-V☆1,073Feb 6, 2024Updated 2 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- ORPSoC fork (from git://openrisc.net/stefan/orpsoc) for de0_nano board with custom made expansion board☆12Sep 26, 2013Updated 13 years ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆53Aug 24, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Source for openrisc.io☆14Jul 9, 2026Updated 3 months ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆387Jul 12, 2017Updated 9 years ago
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 6 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆72Feb 13, 2025Updated last year
- VeeR EL2 Core☆349Updated this week
- newlib OpenRISC development☆27Jul 18, 2026Updated 3 months ago
- The source code that empowers OpenROAD Cloud☆15Jun 29, 2020Updated 6 years ago
- This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…☆572Nov 26, 2024Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,398Sep 7, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆17Nov 25, 2017Updated 8 years ago
- vhdl related contents☆11Apr 27, 2020Updated 6 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 9 years ago
- Verilog based FPGA Design of SHA256 Simulated on ModelSim☆24May 18, 2018Updated 8 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆87Dec 23, 2018Updated 7 years ago
- ☆13Jan 10, 2016Updated 10 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago