openrisc / or1ksim
The OpenRISC 1000 architectural simulator
☆74Updated 7 months ago
Alternatives and similar repositories for or1ksim:
Users that are interested in or1ksim are comparing it to the libraries listed below
- Core description files for FuseSoC☆124Updated 4 years ago
- ☆46Updated 2 weeks ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago
- LatticeMico32 soft processor☆105Updated 10 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 5 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆80Updated 4 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- RISC-V Frontend Server☆63Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆96Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆116Updated 2 years ago
- OpenRISC 1200 implementation☆165Updated 9 years ago
- Yet Another RISC-V Implementation☆91Updated 6 months ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- OpenSPARC-based SoC☆65Updated 10 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 2 years ago
- SystemVerilog Development Environment☆53Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 3 weeks ago
- A port of FreeRTOS for the RISC-V ISA☆75Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- OpenRISC Tutorials☆41Updated 8 months ago
- FuseSoC standard core library☆132Updated 2 weeks ago
- A 32-bit Microcontroller featuring a RISC-V core☆150Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆96Updated 5 years ago