Galland / LEON2Links
LEON2 SPARC CPU IP core LGPL by Gaisler Research
☆18Updated 12 years ago
Alternatives and similar repositories for LEON2
Users that are interested in LEON2 are comparing it to the libraries listed below
Sorting:
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆17Updated 2 months ago
- CMod-S6 SoC☆42Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 6 months ago
- System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files.☆11Updated 12 years ago
- The OpenRISC 1000 architectural simulator☆76Updated last month
- Open Processor Architecture☆26Updated 9 years ago
- FPGA Development for the parallella☆19Updated 7 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆33Updated 10 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Updated 5 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- PulseRain FP51-1T MCU core☆9Updated 7 years ago
- RISC-V System on Chip Builder☆12Updated 4 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆47Updated last month
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 3 weeks ago
- Axiom Alpha prototype software (FPGA, Linux, etc.)☆30Updated 9 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆35Updated 3 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 4 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- Minimal microprocessor☆20Updated 7 years ago
- OpenSPARC-based SoC☆68Updated 10 years ago
- A RISC-V processor☆15Updated 6 years ago
- ☆51Updated 8 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago