Galland / LEON2Links
LEON2 SPARC CPU IP core LGPL by Gaisler Research
☆20Updated 12 years ago
Alternatives and similar repositories for LEON2
Users that are interested in LEON2 are comparing it to the libraries listed below
Sorting:
- LatticeMico32 soft processor☆107Updated 11 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated last year
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated last month
- The OpenRISC 1000 architectural simulator☆75Updated 7 months ago
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- CMod-S6 SoC☆43Updated 7 years ago
- OpenSPARC-based SoC☆74Updated 11 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 6 months ago
- turbo 8051☆29Updated 8 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆69Updated 7 years ago
- ☆63Updated 6 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆78Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- OpenGL-like graphics pipeline on a Xilinx FPGA☆33Updated 15 years ago
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆37Updated 10 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated this week
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Another tiny RISC-V implementation☆61Updated 4 years ago
- Optimized RISC-V FP emulation for 32-bit processors☆36Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.☆36Updated 3 years ago