Galland / LEON2Links
LEON2 SPARC CPU IP core LGPL by Gaisler Research
☆19Updated 12 years ago
Alternatives and similar repositories for LEON2
Users that are interested in LEON2 are comparing it to the libraries listed below
Sorting:
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 8 months ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- CMod-S6 SoC☆42Updated 7 years ago
- OpenSPARC-based SoC☆69Updated 11 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆19Updated last month
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆24Updated 3 years ago
- The OpenRISC 1000 architectural simulator☆76Updated 3 months ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆77Updated 2 years ago
- Another tiny RISC-V implementation☆58Updated 4 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A RISC-V processor☆15Updated 6 years ago
- ☆64Updated 6 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆18Updated 2 years ago
- turbo 8051☆29Updated 7 years ago
- IRSIM switch-level simulator for digital circuits☆34Updated 4 months ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated 2 months ago
- Trivial RISC-V Linux binary bootloader☆51Updated 4 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆31Updated 10 months ago
- A 6800 CPU written in nMigen☆49Updated 4 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A bit-serial CPU☆19Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated 3 weeks ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago