openrisc / or1k-gcc
GCC port for OpenRISC 1000
☆23Updated last month
Alternatives and similar repositories for or1k-gcc:
Users that are interested in or1k-gcc are comparing it to the libraries listed below
- LEON2 SPARC CPU IP core LGPL by Gaisler Research☆18Updated 12 years ago
- The OpenRISC 1000 architectural simulator☆74Updated last week
- Simulation VCD waveform viewer, using old Motif UI☆25Updated 2 years ago
- LatticeMico32 soft processor☆105Updated 10 years ago
- SiFive OpenEmbedded / Yocto BSP Layer☆52Updated 3 weeks ago
- Trivial RISC-V Linux binary bootloader☆50Updated 4 years ago
- ☆22Updated last year
- Software, tools, documentation for Vegaboard platform☆64Updated 5 years ago
- open-source SDKs for the SCR1 core☆74Updated 5 months ago
- SoftCPU/SoC engine-V☆54Updated last month
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆78Updated 2 years ago
- A port of FreeRTOS for the RISC-V ISA☆76Updated 6 years ago
- busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.☆98Updated 10 months ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- PulseRain Rattlesnake - RISCV RV32IMC Soft CPU☆34Updated 5 years ago
- Freecores website☆19Updated 8 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆16Updated 2 years ago
- The development tree for OpenOCD for the Synopsys DesignWare ARC processor family☆14Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆63Updated 7 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 5 months ago
- RISC-V Scratchpad☆66Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆60Updated 5 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- PolarFire SoC yocto Board Support Package☆54Updated last month
- OpenRISC Tutorials☆41Updated 8 months ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆32Updated 10 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- RISC-V Frontend Server☆63Updated 6 years ago