Alternatives and similar repositories for linux

Users that are interested in linux are comparing it to the libraries listed below

• damien-lemoal / buildroot
  buildroot fork
  ☆38Updated 3 months ago
• michaeljclark / busybear-linux
  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.
  ☆98Updated last year
• damien-lemoal / riscv64-nommu-buildroot
  ☆43Updated 4 years ago
• Galland / LEON2
  LEON2 SPARC CPU IP core LGPL by Gaisler Research
  ☆19Updated 12 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆75Updated 5 months ago
• westerndigitalcorporation / RISC-V-Linux
  This repository provides a Linux kernel bootable on RISC-V boards from SiFive
  ☆169Updated 5 years ago
• openrisc / or1k-gcc
  GCC port for OpenRISC 1000
  ☆25Updated 6 months ago
• rwmjones / fedora-riscv-bootstrap
  Bootstrapping Fedora on RISC-V
  ☆29Updated 7 years ago
• tommythorn / yari
  YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…
  ☆44Updated 10 months ago
• mdepx / mdepx
  MDX — A bare-metal / RTOS framework
  ☆27Updated last month
• riscvarchive / riscv-platform-specs
  RISC-V Profiles and Platform Specification
  ☆114Updated 2 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆91Updated 2 years ago
• riscvarchive / riscv-newlib
  RISC-V port of newlib
  ☆100Updated 3 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆63Updated 4 months ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆90Updated 4 years ago
• embecosm / riscv-gdbserver
  GDB Server for interacting with RISC-V models, boards and FPGAs
  ☆20Updated 6 years ago
• openrisc / or1200
  OpenRISC 1200 implementation
  ☆172Updated 9 years ago
• openrisc / tutorials
  OpenRISC Tutorials
  ☆46Updated 2 weeks ago
• jbush001 / RISC-Processor
  32-bit RISC processor
  ☆24Updated 6 years ago
• starfive-tech / JH7100_Docs
  ☆61Updated 4 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆52Updated 4 years ago
• riscvarchive / riscv-poky
  Port of the Yocto Project to the RISC-V ISA
  ☆61Updated 6 years ago
• lcbcFoo / ReonV
  ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…
  ☆77Updated 3 years ago
• westerndigitalcorporation / swerv-ISS
  Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
  ☆202Updated 4 years ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆70Updated 11 years ago
• XUANTIE-RV / buildroot
  Buildroot customized for Xuantie™ RISC-V CPU
  ☆47Updated 3 years ago
• riscvarchive / riscv-binutils-gdb
  RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
  ☆149Updated 3 years ago
• atgreen / moxie-cores
  Moxie-compatible core repository
  ☆47Updated 2 months ago
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆64Updated 5 years ago