aeste / aembLinks
Multi-threaded 32-bit embedded core family.
☆24Updated 12 years ago
Alternatives and similar repositories for aemb
Users that are interested in aemb are comparing it to the libraries listed below
Sorting:
- ☆22Updated last month
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Open Processor Architecture☆26Updated 9 years ago
- OpenFPGA☆34Updated 7 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆42Updated this week
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- ☆27Updated 3 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆63Updated 5 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Advanced Debug Interface☆15Updated 4 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- Yosys Plugins☆21Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆28Updated last month
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last week
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- Torc: Tools for Open Reconfigurable Computing☆38Updated 8 years ago