olgirard / openmsp430Links
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
☆71Updated 7 years ago
Alternatives and similar repositories for openmsp430
Users that are interested in openmsp430 are comparing it to the libraries listed below
Sorting:
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- Wishbone interconnect utilities☆44Updated last month
- LatticeMico32 soft processor☆107Updated 11 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆81Updated 3 years ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Verilog wishbone components☆123Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated last year
- ☆139Updated this week
- A set of Wishbone Controlled SPI Flash Controllers☆95Updated 3 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆101Updated last month
- Basic USB 1.1 Host Controller for small FPGAs☆97Updated 5 years ago
- ☆41Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 5 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆111Updated 6 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆85Updated last year
- Another tiny RISC-V implementation☆64Updated 4 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Verilog implementation of a RISC-V core☆134Updated 7 years ago
- Small (Q)SPI flash memory programmer in Verilog☆68Updated 3 years ago
- Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…☆32Updated 7 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- FuseSoC standard core library☆151Updated last month