The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
☆73Mar 31, 2018Updated 8 years ago
Alternatives and similar repositories for openmsp430
Users that are interested in openmsp430 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆21May 20, 2022Updated 3 years ago
- On the TOCTOU Problem in Remote Attestation☆15Jun 4, 2024Updated last year
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆16Aug 3, 2022Updated 3 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- LatticeMico32 soft processor☆105Oct 10, 2014Updated 11 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 5 years ago
- OpenRISC 1200 implementation☆180Nov 11, 2015Updated 10 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- Docker image with Xilinx FPGA Tools (Vivado - SDAccel) usable with GUI on Mac☆10Oct 6, 2018Updated 7 years ago
- SystemC Design of a Master/Slave I2C Bus☆18Aug 14, 2015Updated 10 years ago
- Minimal microprocessor☆21Jul 1, 2017Updated 8 years ago
- 基于玄铁openc906，搭建最小化SoC系统☆20Apr 7, 2025Updated last year
- Learn, share and collaborate on ASIC design using open tools and technologies☆14Dec 27, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Minimal OpenMSP430 hardware extensions for isolation and attestation☆24May 19, 2025Updated 10 months ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- ☆18Mar 25, 2023Updated 3 years ago
- A header only C++11 library for functional coverage☆36Oct 5, 2022Updated 3 years ago
- ZPUino HDL implementation☆91Aug 6, 2018Updated 7 years ago
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- ☆13Aug 22, 2022Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- open cv software isp study☆17Nov 9, 2020Updated 5 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆26Mar 1, 2021Updated 5 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 5 months ago
- Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module☆20Nov 8, 2017Updated 8 years ago
- M-Kernel embedded RTOS☆14Apr 11, 2013Updated 13 years ago
- Time to Digital Converter (TDC)☆36Dec 27, 2020Updated 5 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆25May 13, 2023Updated 2 years ago
- RTL Verilog library for various DSP modules☆95Feb 17, 2022Updated 4 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- ☆21Jan 25, 2018Updated 8 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆197Oct 9, 2019Updated 6 years ago
- RISC-V CPU Core☆420Jun 24, 2025Updated 9 months ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆15Aug 29, 2022Updated 3 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago