The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
☆73Mar 31, 2018Updated 8 years ago
Alternatives and similar repositories for openmsp430
Users that are interested in openmsp430 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- On the TOCTOU Problem in Remote Attestation☆15Jun 4, 2024Updated last year
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆16Aug 3, 2022Updated 3 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- LatticeMico32 soft processor☆105Oct 10, 2014Updated 11 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- OpenRISC 1200 implementation☆180Nov 11, 2015Updated 10 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 2 years ago
- Docker image with Xilinx FPGA Tools (Vivado - SDAccel) usable with GUI on Mac☆10Oct 6, 2018Updated 7 years ago
- SystemC Design of a Master/Slave I2C Bus☆18Aug 14, 2015Updated 10 years ago
- Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.☆35Jan 17, 2012Updated 14 years ago
- Minimal microprocessor☆21Jul 1, 2017Updated 8 years ago
- 基于玄铁openc906，搭建最小化SoC系统☆21Apr 7, 2025Updated last year
- Learn, share and collaborate on ASIC design using open tools and technologies☆13Dec 27, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Minimal OpenMSP430 hardware extensions for isolation and attestation☆24May 19, 2025Updated last year
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- ☆18Mar 25, 2023Updated 3 years ago
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- A header only C++11 library for functional coverage☆35Oct 5, 2022Updated 3 years ago
- Verilog hardware abstraction library☆53May 12, 2026Updated last week
- ZPUino HDL implementation☆92Aug 6, 2018Updated 7 years ago
- Microbenchmarks for x86_64 kernel entry methods☆20Feb 21, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- ☆13Aug 22, 2022Updated 3 years ago
- RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC☆102Jul 30, 2022Updated 3 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- open cv software isp study☆17Nov 9, 2020Updated 5 years ago
- download from opencores.org☆16May 4, 2018Updated 8 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 6 months ago
- Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module☆20Nov 8, 2017Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- M-Kernel embedded RTOS☆14Apr 11, 2013Updated 13 years ago
- Time to Digital Converter (TDC)☆36Dec 27, 2020Updated 5 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆26May 13, 2023Updated 3 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- ☆21Jan 25, 2018Updated 8 years ago
- RTL Verilog library for various DSP modules☆97Feb 17, 2022Updated 4 years ago