olgirard / openmsp430
The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
☆58Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for openmsp430
- SoftCPU/SoC engine-V☆54Updated last year
- Wishbone interconnect utilities☆37Updated 5 months ago
- Featherweight RISC-V implementation☆52Updated 2 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆64Updated 2 years ago
- Spen's Official OpenOCD Mirror☆48Updated 8 months ago
- Yet Another RISC-V Implementation☆85Updated 2 months ago
- LatticeMico32 soft processor☆102Updated 10 years ago
- RISCV model for Verilator/FPGA targets☆45Updated 5 years ago
- Demo SoC for SiliconCompiler.☆52Updated 3 weeks ago
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆69Updated 7 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆66Updated this week
- TCP/IP controlled VPI JTAG Interface.☆60Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- FuseSoC standard core library☆115Updated last month
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 10 months ago
- Verilog implementation of a RISC-V core☆102Updated 6 years ago
- ☆37Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆33Updated 4 years ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- Naive Educational RISC V processor☆74Updated last month
- A wishbone controlled scope for FPGA's☆73Updated 10 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- JTAG DPI module for OpenRISC simulation with Verilator☆16Updated 12 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 5 years ago
- Reusable Verilog 2005 components for FPGA designs☆36Updated last year
- Another tiny RISC-V implementation☆52Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago