The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
☆74Mar 31, 2018Updated 8 years ago
Alternatives and similar repositories for openmsp430
Users that are interested in openmsp430 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- On the TOCTOU Problem in Remote Attestation☆15Jun 4, 2024Updated 2 years ago
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆16Aug 3, 2022Updated 4 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- A Python package for creating and solving constrained randomization problems.☆19Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- OpenRISC 1200 implementation☆181Nov 11, 2015Updated 10 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated last year
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 3 years ago
- Docker image with Xilinx FPGA Tools (Vivado - SDAccel) usable with GUI on Mac☆10Oct 6, 2018Updated 7 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- SystemC Design of a Master/Slave I2C Bus☆18Aug 14, 2015Updated 10 years ago
- Minimal microprocessor☆21Jul 1, 2017Updated 9 years ago
- ☆11Mar 3, 2022Updated 4 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- LatticeMico32 soft processor☆105Oct 10, 2014Updated 11 years ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 12 years ago
- Minimal OpenMSP430 hardware extensions for isolation and attestation☆24May 19, 2025Updated last year
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- ☆19Mar 25, 2023Updated 3 years ago
- A header only C++11 library for functional coverage☆35Oct 5, 2022Updated 3 years ago
- A modular hardware abstraction library☆55Aug 3, 2026Updated last week
- Wishbone controlled I2C controllers☆59Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Utilities for MyHDL☆19Dec 15, 2023Updated 2 years ago
- ☆13Aug 22, 2022Updated 3 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- open cv software isp study☆18Nov 9, 2020Updated 5 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆35May 17, 2020Updated 6 years ago
- Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.☆36Jan 17, 2012Updated 14 years ago
- Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module☆20Nov 8, 2017Updated 8 years ago
- Time to Digital Converter (TDC)☆38Dec 27, 2020Updated 5 years ago
- M-Kernel embedded RTOS☆14Apr 11, 2013Updated 13 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Chisel3 AXI4-{Lite, Full, Stream} Definitions☆15Dec 31, 2018Updated 7 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 9 months ago
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- RTL Verilog library for various DSP modules☆99Feb 17, 2022Updated 4 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆25May 13, 2023Updated 3 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆206Oct 9, 2019Updated 6 years ago
- A migration for the page table entry based side-channel attack agains SGX enclaves.☆19Feb 10, 2025Updated last year