Alternatives and similar repositories for harv

Users that are interested in harv are comparing it to the libraries listed below

• buttercutter / DDR
  A simple DDR3 memory controller
  ☆58Updated 2 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆66Updated 3 weeks ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated this week
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 9 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆108Updated this week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆21Updated last month
• verilator / example-systemverilog
  ☆40Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆62Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆57Updated 2 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 8 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆73Updated 3 weeks ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 5 months ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• UofT-HPRC / Tbps_CRC
  A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second
  ☆16Updated last year
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆24Updated last month
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆72Updated last month
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last week
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• stnolting / riscv-debug-dtm
  🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
  ☆26Updated 2 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆45Updated last year
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆28Updated last year