pulp-platform / gpioLinks
Parametric GPIO Peripheral
☆11Updated 8 months ago
Alternatives and similar repositories for gpio
Users that are interested in gpio are comparing it to the libraries listed below
Sorting:
- Another tiny RISC-V implementation☆59Updated 4 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated last week
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Updated 7 years ago
- ☆30Updated 3 weeks ago
- Platform Level Interrupt Controller☆43Updated last year
- svlib from http://www.verilab.com/resources/svlib/☆24Updated 5 years ago
- pulp_soc is the core building component of PULP based SoCs☆80Updated 7 months ago
- Cortex-M0 DesignStart Wrapper☆20Updated 6 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 11 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Simple runtime for Pulp platforms☆49Updated 2 weeks ago
- ☆32Updated this week
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆12Updated 3 weeks ago
- turbo 8051☆29Updated 8 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- Generic Register Interface (contains various adapters)☆130Updated 2 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 3 years ago
- DSP WishBone Compatible Cores☆14Updated 11 years ago
- RISC-V Verification Interface☆107Updated 3 weeks ago
- ☆15Updated 10 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 11 months ago