An RTL-to-Chip Silicon Design Solution.
☆47Jul 14, 2026Updated this week
Alternatives and similar repositories for ecos-studio
Users that are interested in ecos-studio are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆36Jun 25, 2026Updated 2 weeks ago
- nscscc2024,HPU河南理工大学参赛作品,两仪处理器☆13Aug 24, 2024Updated last year
- ☆21May 26, 2025Updated last year
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆15Updated this week
- The official website of One Student One Chip project.☆12Feb 5, 2026Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Build mini linux for your own RISC-V emulator!☆24Sep 11, 2024Updated last year
- Mirror of https://gitee.com/loongson-edu/open-la500.git☆27Jan 2, 2025Updated last year
- ☆20Updated this week
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆25Dec 8, 2025Updated 7 months ago
- ☆40Jul 22, 2025Updated 11 months ago
- RTL-to-Vector-to-GDS☆84Apr 2, 2026Updated 3 months ago
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- An open-source EDA infrastructure and tools from netlist to GDS☆524Updated this week
- ☆25Aug 11, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 本项目已被合并至官方Chiplab中☆14Jan 13, 2025Updated last year
- Custom IC Design Platform☆105Updated this week
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆94Aug 29, 2023Updated 2 years ago
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- Python超星尔雅学习通小工具-答题助手☆15Oct 12, 2023Updated 2 years ago
- Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.☆17Apr 13, 2023Updated 3 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆30Oct 3, 2023Updated 2 years ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆251Jun 30, 2026Updated 2 weeks ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆41Jun 10, 2021Updated 5 years ago
- ☆63Mar 31, 2025Updated last year
- A tapeout-ready structure for hierarchical analog design (v0.1).☆26Jan 16, 2026Updated 5 months ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆19Oct 4, 2022Updated 3 years ago
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆22Apr 1, 2025Updated last year
- Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920☆36Jun 1, 2026Updated last month
- Nix flake for more up-to-date versions of EDA tools☆28Updated this week
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd. (ICS55 for short).☆244Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆133May 8, 2026Updated 2 months ago
- ☆16Jul 23, 2025Updated 11 months ago
- GPU-based logic synthesis tool☆107Mar 31, 2026Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆92Updated this week
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Apr 20, 2026Updated 2 months ago
- Basic chisel difftest environment for RTL design (WIP☆21Mar 8, 2025Updated last year
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆17Apr 27, 2026Updated 2 months ago