newaetech / sonata-pcbLinks
Design files and associated documentation for Sonata PCB, part of the Sunburst Project
☆19Updated 9 months ago
Alternatives and similar repositories for sonata-pcb
Users that are interested in sonata-pcb are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆85Updated 2 months ago
- Python script to transform a VCD file to wavedrom format☆82Updated 3 years ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆69Updated 3 months ago
- FuseSoC standard core library☆151Updated last month
- Test dashboard for verification features in Verilator☆28Updated this week
- Python-based IP-XACT parser☆142Updated last year
- Playing around with Formal Verification of Verilog and VHDL☆64Updated 4 years ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆128Updated 3 weeks ago
- A SystemVerilog source file pickler.☆60Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 11 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆60Updated last month
- ☆111Updated 2 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆54Updated last week
- Spen's Official OpenOCD Mirror☆51Updated 10 months ago
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- HW Design Collateral for Caliptra RoT IP☆124Updated last week
- RISC-V Nox core☆71Updated 5 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆63Updated last month
- Open source ISS and logic RISC-V 32 bit project☆61Updated last month
- SystemVerilog synthesis tool☆223Updated 10 months ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆135Updated last month
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆25Updated 6 months ago
- An open-source HDL register code generator fast enough to run in real time.☆81Updated 3 weeks ago
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆146Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago