newaetech / sonata-pcbLinks
Design files and associated documentation for Sonata PCB, part of the Sunburst Project
☆18Updated 5 months ago
Alternatives and similar repositories for sonata-pcb
Users that are interested in sonata-pcb are comparing it to the libraries listed below
Sorting:
- A demo system for Ibex including debug support and some peripherals☆76Updated 3 months ago
- Playing around with Formal Verification of Verilog and VHDL☆62Updated 4 years ago
- SystemVerilog Linter based on pyslang☆31Updated 4 months ago
- Open source ISS and logic RISC-V 32 bit project☆57Updated 3 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆57Updated 2 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 7 months ago
- Python script to transform a VCD file to wavedrom format☆79Updated 3 years ago
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Updated 6 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- HW Design Collateral for Caliptra RoT IP☆110Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- Naive Educational RISC V processor☆88Updated last month
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated last month
- ☆34Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆49Updated this week
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆65Updated last month
- Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!☆40Updated 3 weeks ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- ☆27Updated this week
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆113Updated last week
- ☆64Updated 4 months ago
- An open-source HDL register code generator fast enough to run in real time.☆73Updated 3 weeks ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆71Updated last month
- Building and deploying container images for open source electronic design automation (EDA)☆116Updated 11 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆108Updated 4 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆47Updated last week
- Control and status register code generator toolchain☆143Updated 2 weeks ago
- RISC-V Nox core☆68Updated last month
- SystemVerilog synthesis tool☆209Updated 6 months ago