Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation
☆14Apr 25, 2020Updated 6 years ago
Alternatives and similar repositories for Wireline-ChModel-Matlab
Users that are interested in Wireline-ChModel-Matlab are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Apr 25, 2020Updated 6 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆17Apr 25, 2020Updated 6 years ago
- Python library for SerDes modelling☆97Jul 18, 2024Updated 2 years ago
- Python implementation of COM, as per IEEE 802.3-22 Annex 93A.☆20Jun 22, 2026Updated 2 months ago
- ☆41Jul 2, 2024Updated 2 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- An FPGA-accelerated platform for FEC analysis of wireline systems☆14Jan 21, 2025Updated last year
- Circuit Toolbox for Matlab/Octave☆20Jun 18, 2015Updated 11 years ago
- GPTIPS2F: Symbolic Regression toolbox for MATLAB evolved☆11Apr 29, 2026Updated 4 months ago
- Open Source RFIC Inductor and Transformer Layout Generation Toolkit☆24Jun 2, 2026Updated 3 months ago
- Analog HDL Design Full-stack Agents☆22Jun 8, 2026Updated 3 months ago
- Keysight Advanced Design System (ADS) to Matlab interface☆59Mar 12, 2022Updated 4 years ago
- Model SAR ADC with python!☆22Jul 8, 2022Updated 4 years ago
- pystateye - A Python Implementation of Statistical Eye Analysis and Visualization☆21May 25, 2024Updated 2 years ago
- An EDA tool for automatic device sizing using Gm/Id method.☆18Jan 10, 2026Updated 8 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- .Net Mail Server based on Lumisoft opensource project☆14Jul 27, 2016Updated 10 years ago
- AWGN signal generator IP for FPGA implemented by Verilog HDL with Fmax up to 320MHz on Xilinx Virtex Ultra-Scale FPGA.☆15Sep 20, 2020Updated 6 years ago
- Conjuntos de funciones realizadas y recopiladas por mí durante la carrera.☆11Aug 2, 2022Updated 4 years ago
- Learn how to use node-serialport in web front project☆11Sep 6, 2019Updated 7 years ago
- Matlab code for coupling matrix synthesis and rotation(已对耦合矩阵综合部分的代码进行了更新,请参考库:Standard-Coupling-Matrix-Synthesis-Code标准化耦合矩阵综合代码)☆14Aug 5, 2024Updated 2 years ago
- ☆17Nov 21, 2016Updated 9 years ago
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- CentOS/Linux 安装shadowsocks 翻墙☆14Oct 24, 2025Updated 10 months ago
- Paradox Game data file parser☆12Aug 7, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆34Feb 21, 2019Updated 7 years ago
- Python package for design and simulation of RF phase-locked loops☆15Apr 23, 2022Updated 4 years ago
- SDR is fun.☆37May 27, 2024Updated 2 years ago
- An open-source C++ library for computing Green's functions for layered media☆39Sep 3, 2026Updated 2 weeks ago
- StatOpt Tool in Python☆21Aug 10, 2026Updated last month
- Free open source Wi-Fi project☆30Feb 4, 2026Updated 7 months ago
- Online save editor for the game Shattered Pixel Dungeon☆24Apr 28, 2026Updated 4 months ago
- Log file scanner used with EDA tools to classify errors and warnings☆13Nov 14, 2022Updated 3 years ago
- Space CACD☆11Oct 16, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC☆29Jun 12, 2018Updated 8 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 10 months ago
- Gaussian noise generator Verilog IP core☆35Jul 5, 2026Updated 2 months ago
- An asset which include circuit symbols for drawing schematics and block diagrams with Affinity Designer☆37Sep 8, 2026Updated last week
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Modem Design☆21May 27, 2020Updated 6 years ago
- 存档车祸警示录发布的所有下架影片☆15Updated this week