tchancarusone / Wireline-ChModel-MatlabLinks
Repository of Matlab tools for analysis of wireline signal integrity and transceiver simulation
☆12Updated 5 years ago
Alternatives and similar repositories for Wireline-ChModel-Matlab
Users that are interested in Wireline-ChModel-Matlab are comparing it to the libraries listed below
Sorting:
- pystateye - A Python Implementation of Statistical Eye Analysis and Visualization☆15Updated last year
- Python library for SerDes modelling☆79Updated last year
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆26Updated last year
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆26Updated 6 years ago
- StatOpt Tool in Python☆16Updated 2 years ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Updated 6 years ago
- Model SAR ADC with python!☆22Updated 3 years ago
- Basic Simulink Blocks for modeling CDRs and PLLs☆13Updated 5 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Updated 5 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆80Updated 2 years ago
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆48Updated 5 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆66Updated this week
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆80Updated 2 years ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆38Updated 3 years ago
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆11Updated 3 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆55Updated 8 years ago
- Python implementation of COM, as per IEEE 802.3-22 Annex 93A.☆16Updated 5 months ago
- ☆24Updated last year
- An EDA tool for automatic device sizing using Gm/Id method.☆14Updated last week
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆175Updated 3 months ago
- A 10bit SAR ADC in Sky130☆27Updated 3 years ago
- Simulink model for noise shaping SAR ADC☆12Updated 5 years ago
- BAG framework☆31Updated last year
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆76Updated 2 months ago
- An FPGA-accelerated platform for FEC analysis of wireline systems☆11Updated 11 months ago
- A tiny Python package to parse spice raw data files.☆53Updated 3 years ago
- Automatic generation of real number models from analog circuits☆48Updated last year
- Low Density Parity Check Decoder☆18Updated 9 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Updated 2 years ago