☆27Feb 27, 2021Updated 5 years ago
Alternatives and similar repositories for AES-Core-engine-
Users that are interested in AES-Core-engine- are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- C++ and Verilog to implement AES128☆24Apr 30, 2018Updated 8 years ago
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆18Dec 16, 2017Updated 8 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- AES-128 Encryption☆11Jul 17, 2014Updated 11 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆141Jul 31, 2022Updated 3 years ago
- This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) al…☆17May 2, 2013Updated 13 years ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 11 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- Vivado board files for the Kintex 7 HPC V2 FPGA board.☆25Jul 31, 2020Updated 5 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆27Aug 1, 2018Updated 7 years ago
- Repository for the course "Sensor Fusion and Non-Linear Filtering" - SSY345 at Chalmers University of Technology☆13May 19, 2019Updated 7 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- A port of the OPL3 to the Panologic G1 thin client☆20Dec 24, 2019Updated 6 years ago
- FLIX-V: FPGA, Linux and RISC-V☆42Nov 5, 2023Updated 2 years ago
- Whisk: 16-bit serial processor for TT02☆13Sep 30, 2024Updated last year
- This is a mirror of https://git.parabola.nu/parabola-cross-bootstrap.git/☆11Dec 9, 2018Updated 7 years ago
- MicroCLI: A command-line interface (CLI) for the STM32F0-Discovery☆12Jan 16, 2013Updated 13 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆14Mar 5, 2017Updated 9 years ago
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 6 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A conda-smithy repository for memory_profiler.☆12Apr 22, 2026Updated last month
- Advanced Machine Learning and Signal Processing IBM☆18Sep 6, 2019Updated 6 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- Cachebench, with hacks to make it run on SmartOS / x86.☆11Feb 15, 2012Updated 14 years ago
- A FPGA implementation of the NTP and NTS protocols☆65May 31, 2023Updated 2 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- ☆15May 17, 2025Updated last year
- Very basic real time operating system for embedded systems...☆18Sep 19, 2020Updated 5 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆40Feb 4, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- CH32V003 is an ultra-cheap RISC-V MCU with 2KB SRAM, 16KB flash, and up to 18 GPIOs☆16Jan 21, 2023Updated 3 years ago
- A LiteX module implementing a USB UAC2 module with simple PDM in/out☆16Feb 16, 2022Updated 4 years ago
- This is the final project for the BP NN FPGA implementation☆11Jan 14, 2017Updated 9 years ago
- Package for dynamic programming☆13Jun 23, 2020Updated 5 years ago
- ☆10Aug 10, 2020Updated 5 years ago
- ☆19Dec 19, 2018Updated 7 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago