sathvikbhat / vlsi_physical_design_automation

Related projects ⓘ

Alternatives and complementary repositories for vlsi_physical_design_automation

• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆32Updated 7 months ago
• magical-eda / UT-AnLay
  Analog Placement Quality Prediction
  ☆19Updated last year
• baloneymath / AncstrGNN
  ☆15Updated 3 years ago
• ABKGroup / PlacementEssentialReadings
  ☆49Updated 3 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆32Updated 4 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• PKU-IDEA / SAGERoute
  SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility (DATE2023)
  ☆19Updated last year
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆63Updated 2 months ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated last year
• UMN-EDA / BeGAN-benchmarks
  ☆25Updated last year
• ABKGroup / PROBE3.0
  ☆36Updated 7 months ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆25Updated last year
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 5 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆77Updated 11 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• vaughnbetz / COFFE
  ☆38Updated last month
• The-OpenROAD-Project / asap7
  ☆97Updated 3 months ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆19Updated this week
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆31Updated last week
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆75Updated last week
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆28Updated 2 years ago
• liangrj2014 / ISPD24_contest
  ☆20Updated last month
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 2 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆23Updated 4 years ago
• muhammadaldacher / Layout-Design-of-an-8x8-SRAM-array
  The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…
  ☆63Updated 2 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆68Updated 6 years ago
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆13Updated 2 years ago
• bu-icsg / TAP-2.5D
  ☆23Updated 3 years ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago