thu-cs-lab / jieplagLinks
Plagiarism detection tool in Rust (inspired by Stanford Moss)
☆54Updated 4 months ago
Alternatives and similar repositories for jieplag
Users that are interested in jieplag are comparing it to the libraries listed below
Sorting:
- Project template for Artix-7 based Thinpad board☆52Updated 4 months ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Updated 3 years ago
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Updated 3 years ago
- Tsinghua Advanced Networking Labs on FPGA☆39Updated last year
- Follow nginx log, and find out bad guys!☆23Updated this week
- ☆11Updated last year
- An optimizing compiler targeting armv7 and risc-v32☆63Updated last year
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Updated last year
- A simple Docker-based build & judge system for complex multi-file projects. 使用 Docker 隔离的适用于多文件项目的自动评测机。☆44Updated 3 years ago
- A summary of my projects☆49Updated last month
- An awesome language and its compiler.☆35Updated 3 years ago
- Documentation for Router Lab☆70Updated 2 months ago
- 2023/12/22 电三 420 每周会议技术分享:「容器」的 slides 和附件☆10Updated 2 years ago
- An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.☆49Updated 3 years ago
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- 支持 USTC 统一身份认证系统鉴权的反向代理,让你的网站只有科大人可以访问☆27Updated 4 years ago
- A compiler that translates SysY (a subset of C language) into ARMv7a, implemented in Java15.☆65Updated 4 years ago
- My DAC '21 work open-sourced.☆14Updated 4 years ago
- Warning: 🕳 ahead!☆16Updated 6 years ago
- A toy compiler written in C++17 that translates SysY (a C-like toy language) into ARM-v7a assembly.☆146Updated 4 years ago
- A compiler for a C-like toy language (named "SysY") into ARMv7a assembly, written in C++17☆50Updated 5 years ago
- My knowledge base☆78Updated this week
- ChatGPT Telegram bot☆53Updated last month
- An open-source anonymous forum frontend.☆55Updated 4 years ago
- 计算机组成原理课程32位监控程序☆50Updated 5 years ago
- 我,秦始皇,打钱!可以开发票。☆56Updated last year
- OS Tutorial Summer of Code 2020☆19Updated 3 years ago
- A router IP written in Verilog.☆12Updated 6 years ago
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- 《计算机设计与实践》测试框架☆17Updated 3 years ago