A naive verilog/systemverilog formatter
☆21Mar 22, 2025Updated last year
Alternatives and similar repositories for verilog-format
Users that are interested in verilog-format are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A router IP written in Verilog.☆12Dec 20, 2019Updated 6 years ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 6 years ago
- 网络学堂 PC 端 App☆21Mar 12, 2026Updated last week
- Project template for Artix-7 based Thinpad board☆52Sep 13, 2025Updated 6 months ago
- Convert regex(es) to dfa.☆14Apr 30, 2021Updated 4 years ago
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 3 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- A utility to clone all files from learn.tsinghua.edu.cn☆30Mar 14, 2026Updated last week
- A hand-written recursive decent Verilog parser.☆10Jan 30, 2026Updated last month
- Compiling finite generators to digital logic. WIP☆13Aug 24, 2020Updated 5 years ago
- Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…☆14Jun 29, 2020Updated 5 years ago
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Nov 29, 2019Updated 6 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- A hardware accelerated IP packet forwarder running on programmable ICs☆15Jan 21, 2023Updated 3 years ago
- My knowledge base☆84Updated this week
- An SoC with multiple RISC-V IMA processors.☆19Aug 1, 2018Updated 7 years ago
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- Warning: 🕳 ahead!☆16Jan 8, 2020Updated 6 years ago
- An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.☆49Mar 29, 2022Updated 3 years ago
- A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.☆30May 14, 2020Updated 5 years ago
- Implementation of several grid routers in Rust☆13Feb 28, 2026Updated 3 weeks ago
- Yet Another AsYnc runtime for RuSt.☆33Feb 1, 2020Updated 6 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- THU Bell on macOS☆28Feb 24, 2020Updated 6 years ago
- Lab for Network Principles since 2019-2020 fall☆174Sep 22, 2025Updated 6 months ago
- Operating System Simulator☆18Jun 18, 2019Updated 6 years ago
- 基于Mastodon的分布式高校封闭平台☆45Jun 12, 2023Updated 2 years ago
- A .NET implementation of TEA, XTEA and XXTEA algorithm.☆17Oct 9, 2019Updated 6 years ago
- CTF - Jarvis OJ 我的题解☆36Aug 11, 2019Updated 6 years ago
- A simple USB to UART board designed with KiCad.☆14May 4, 2023Updated 2 years ago
- 开源软件供应链点亮计划 - 暑期2020的主页代码。This repository is the homepage for Open Source Promotion Plan - Summer 2020 built with create-react-app.☆10Aug 28, 2024Updated last year
- CIDR union / subtraction☆14Mar 13, 2026Updated last week
- Implements kernels with RISC-V Vector☆22Mar 24, 2023Updated 3 years ago
- An advanced cross-platform serial port utility☆27Dec 28, 2025Updated 2 months ago
- An implementation of "Efficient Gradient-Domain Compositing Using Quadtrees", SIGGRAPH 2007.☆25Jan 9, 2020Updated 6 years ago
- ☆20Dec 11, 2024Updated last year
- Documentation for Router Lab☆70Nov 19, 2025Updated 4 months ago
- 在线图书借阅系统 - 2017 THU OOP课大作业☆13Jul 1, 2018Updated 7 years ago
- Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University☆11Jun 9, 2019Updated 6 years ago