dramforever / finlogLinks
Compiling finite generators to digital logic. WIP
☆14Updated 4 years ago
Alternatives and similar repositories for finlog
Users that are interested in finlog are comparing it to the libraries listed below
Sorting:
- (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog☆12Updated 3 years ago
- ☆23Updated 2 years ago
- A mini (consistent-wannabe) proof-assistant with power roughly equivalent to intelligence of a two month old cat☆17Updated 3 years ago
- A Collection of Papers & Notes in Programming Language & Formal Verification☆17Updated 3 years ago
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- Convert shared libraries into relocatable objects☆10Updated last year
- Just for fun riscv64 emulator, which boots the Linux.☆41Updated 2 years ago
- Yet Another AsYnc runtime for RuSt.☆34Updated 5 years ago
- Relaxed Rust (for cats)☆16Updated 5 years ago
- A router IP written in Verilog.☆13Updated 5 years ago
- Python3 auto-active verification library (migrated to an Intel project)☆25Updated 3 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- RV32I by cats☆16Updated last year
- Dockerfile with Vivado for CI☆28Updated 5 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- OS Tutorial Summer of Code 2020☆19Updated 3 years ago
- 🚧施工中🚧 用 Arend 写证明的交互式教程