Alternatives and similar repositories for naiverouter

Users that are interested in naiverouter are comparing it to the libraries listed below

• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• MashPlant / decaf-rs
  Framework of pa code for THU compiler principle course.
  ☆13Updated 5 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• Harry-Chen / HERMES
  HERMES: sHallow dirEctory stRucture Many-filE fileSystem
  ☆20Updated 5 years ago
• TrivialCompiler / Talk
  Tex source for talk slide.
  ☆10Updated 4 years ago
• thu-cs-lab / tanlabs
  Tsinghua Advanced Networking Labs on FPGA
  ☆38Updated 7 months ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 5 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• CircuitCoder / MeowRust
  Relaxed Rust (for cats)
  ☆16Updated 5 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 2 months ago
• were / bfsh
  Being a full-stack hacker, RISCV, LLVM, and more.
  ☆17Updated 3 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆46Updated 2 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• jiegec / Projects
  A summary of my projects
  ☆49Updated 2 months ago
• JohndeVostok / APE
  A GPU FP32 computation method with Tensor Cores.
  ☆20Updated 2 years ago
• oscomp / proj6-user-level-interrupt
  基于FPGA实现用户态中断硬件机制与优化操作系统内核
  ☆9Updated 2 months ago
• jiegec / learn_tsinghua_app
  网络学堂 PC 端 App
  ☆21Updated 2 years ago
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated last year
• Fugoes / ctrj
  Compile Time RapidJSON: A compile time C++ header only JSON library without bloating yet another hand-crafted JSON parser based on RapidJ…
  ☆15Updated 4 years ago
• LyricZhao / ThinRouter
  A SystemVerilog implementation of MIPS32 CPU and RIP router
  ☆23Updated 5 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• yukiiiteru / DailySchedule_2020
  OS Tutorial Summer of Code 2020
  ☆19Updated 2 years ago
• jiegec / SPECCPU2017Harmony
  Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT
  ☆15Updated 4 months ago
• MashPlant / lalr1
  An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.
  ☆48Updated 3 years ago
• thu-cs-lab / TCP-Lab-Docs
  Documentation for TCP Lab
  ☆12Updated last week