Alternatives and similar repositories for tanlabs

Users that are interested in tanlabs are comparing it to the libraries listed below

• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• meow-chip / MeowRouter
  A hardware accelerated IP packet forwarder running on programmable ICs
  ☆16Updated 2 years ago
• jiegec / kb
  My knowledge base
  ☆66Updated last month
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆48Updated 2 years ago
• jiegec / Projects
  A summary of my projects
  ☆49Updated 2 months ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 5 years ago
• Harry-Chen / TrivialTomasulo
  Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University
  ☆11Updated 6 years ago
• twd2 / roload
  My DAC '21 work open-sourced.
  ☆14Updated 4 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆50Updated 5 years ago
• thu-cs-lab / Router-Lab-Docs
  Documentation for Router Lab
  ☆68Updated last week
• thu-cs-lab / jieplag
  Plagiarism detection tool in Rust (inspired by Stanford Moss)
  ☆52Updated 5 months ago
• twd2 / fpga-nat64
  A four-10gbe-port dual-stack router with IPv4 and IPv6 translation support.
  ☆31Updated 5 years ago
• MashPlant / lalr1
  An LALR1(1)/LL(1) parser generator in Rust, for multiple languages.
  ☆48Updated 3 years ago
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 5 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• thu-cs-lab / supervisor-rv
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆120Updated 11 months ago
• Harry-Chen / HERMES
  HERMES: sHallow dirEctory stRucture Many-filE fileSystem
  ☆20Updated 6 years ago
• madsys-dev / syscall_intercept
  The system call intercepting library
  ☆22Updated 2 years ago
• typekernel / typekernel
  Warning: 🕳 ahead!
  ☆16Updated 5 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• trivialmips / linux-nontrivial-mips
  Linux porting to NonTrivialMIPS (based on linux-stable)
  ☆12Updated 6 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• MashPlant / decaf-rs
  Framework of pa code for THU compiler principle course.
  ☆13Updated 5 years ago
• thu-cs-lab / Router-Lab
  Lab for Network Principles since 2019-2020 fall
  ☆175Updated 9 months ago
• Oyami-Srk / RISCV-GDB-Paging
  Paging Debug tool for GDB using python
  ☆13Updated 3 years ago
• yukiiiteru / DailySchedule_2020
  OS Tutorial Summer of Code 2020
  ☆19Updated 3 years ago
• skyzh / linux-kernel-labs
  Linux kernel labs
  ☆55Updated 4 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• jiegec / SPECCPU2017Harmony
  Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT
  ☆26Updated 2 months ago