mattvenn / flipflop_demoLinks
Flip flop setup, hold & metastability explorer tool
☆34Updated 2 years ago
Alternatives and similar repositories for flipflop_demo
Users that are interested in flipflop_demo are comparing it to the libraries listed below
Sorting:
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- ☆33Updated 2 years ago
- ☆33Updated 4 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆38Updated 3 weeks ago
- A padring generator for ASICs☆25Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- ☆39Updated 2 years ago
- Small footprint and configurable SPI core☆42Updated last week
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- ☆36Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆6Updated last week
- sample VCD files☆37Updated last year
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated last week
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 6 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆113Updated 3 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆45Updated last year
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 4 months ago
- SAR ADC on tiny tapeout☆39Updated 4 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated 2 weeks ago
- USB virtual model in C++ for Verilog☆30Updated 7 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated this week
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆17Updated 2 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆67Updated 8 months ago