mattvenn / flipflop_demoLinks
Flip flop setup, hold & metastability explorer tool
☆48Updated 2 years ago
Alternatives and similar repositories for flipflop_demo
Users that are interested in flipflop_demo are comparing it to the libraries listed below
Sorting:
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆115Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated last week
- Drawio => VHDL and Verilog☆57Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 9 months ago
- ☆79Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated last week
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆56Updated this week
- submission repository for efabless mpw6 shuttle☆30Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆53Updated 3 months ago
- ☆42Updated 3 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- Python script to transform a VCD file to wavedrom format☆80Updated 3 years ago
- ☆26Updated 2 years ago
- End-to-End Open-Source I2C GPIO Expander☆33Updated last month
- A padring generator for ASICs☆25Updated 2 years ago
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆48Updated 2 years ago
- ☆39Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated last month
- Fabric generator and CAD tools graphical frontend☆14Updated last month
- SAR ADC on tiny tapeout☆42Updated 7 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- A compact, configurable RISC-V core☆11Updated last month
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- An open-source HDL register code generator fast enough to run in real time.☆73Updated 3 weeks ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 5 months ago