Alternatives and similar repositories for flipflop_demo:

Users that are interested in flipflop_demo are comparing it to the libraries listed below

• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆27Updated 2 months ago
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆4Updated 4 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆39Updated last month
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆21Updated last year
• FPGA-Research / FABulator
  Fabric generator and CAD tools graphical frontend
  ☆12Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆24Updated last month
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last week
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated last year
• wavedrom / vcd-samples
  sample VCD files
  ☆36Updated last year
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 5 months ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆50Updated 2 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• yrrapt / analogue_design_example
  An example of analogue design using open source IC design tools
  ☆29Updated 3 years ago
• aesc-silicon / i2c-gpio-expander
  End-to-End Open-Source I2C GPIO Expander
  ☆31Updated last week
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆15Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 3 months ago
• mattvenn / openlane_summary
  ☆20Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• yrrapt / caravel_amsat_txrx_ic
  ☆30Updated 4 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago