mattvenn / flipflop_demo
Flip flop setup, hold & metastability explorer tool
☆34Updated 2 years ago
Alternatives and similar repositories for flipflop_demo:
Users that are interested in flipflop_demo are comparing it to the libraries listed below
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated 3 weeks ago
- Extensible FPGA control platform☆59Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆59Updated this week
- ☆39Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- Virtual development board for HDL design☆41Updated 2 years ago
- SAR ADC on tiny tapeout☆39Updated 2 months ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆110Updated 3 years ago
- USB virtual model in C++ for Verilog☆29Updated 6 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆29Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆27Updated 2 months ago
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- ☆33Updated 4 years ago
- ☆36Updated 2 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆4Updated this week
- End-to-End Open-Source I2C GPIO Expander☆31Updated 3 weeks ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- ☆33Updated 2 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆25Updated last month
- ☆34Updated 5 months ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆27Updated 3 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated last year
- assorted library of utility cores for amaranth HDL☆87Updated 6 months ago
- ☆26Updated last year
- sample VCD files☆36Updated last year