Alternatives and similar repositories for flipflop_demo

Users that are interested in flipflop_demo are comparing it to the libraries listed below

• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated this week
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆98Updated last week
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆8Updated 2 months ago
• wavedrom / vcd-samples
  sample VCD files
  ☆37Updated 2 weeks ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• olofk / vidbo
  Virtual Development Board
  ☆60Updated 3 years ago
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆18Updated 4 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated last week
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 4 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 6 months ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆56Updated last year
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆28Updated 6 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆30Updated 4 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆52Updated 2 months ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆81Updated 5 years ago
• pieter3d / simview
  ☆79Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆63Updated 2 weeks ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆57Updated 2 weeks ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆49Updated last month