This projects contains Veriolg code and timing analysis of a asynchronous FIFO. The README.md document is maintained, which explains every aspects of the code.
☆51Jul 29, 2024Updated 2 years ago
Alternatives and similar repositories for Async_FIFO_Design
Users that are interested in Async_FIFO_Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository consists of all chipdev.io practice questions☆30Oct 11, 2023Updated 2 years ago
- opensource EDA tool flor VLSI design☆38Sep 17, 2023Updated 2 years ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆38Jan 23, 2024Updated 2 years ago
- This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of …☆41Sep 21, 2023Updated 2 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- design of LMS adaptive 4-tap FIR filter using Distributed Arithmetic architecture in verilog☆10Sep 26, 2022Updated 3 years ago
- use Zybo z7-20☆17May 21, 2025Updated last year
- Digital audio equalizer created written in Verilog for Altera DE1 SoC FPGA board.☆12Aug 9, 2019Updated 7 years ago
- This repository contains the design files of RISC-V Pipeline Core☆75May 11, 2023Updated 3 years ago
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- ☆22Oct 20, 2025Updated 10 months ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆10Feb 27, 2023Updated 3 years ago
- ☆25Nov 4, 2023Updated 2 years ago
- Simple Python parser for extracting HDL (VHDL or Verilog) documentation☆25Mar 1, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Jan 1, 2023Updated 3 years ago
- Verilog implementation of a ultrasonic radar☆20Jan 7, 2018Updated 8 years ago
- AHB-APB Bridge RTL Design☆16Apr 19, 2018Updated 8 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆72Apr 13, 2024Updated 2 years ago
- ⭐ A curated list of my GitHub starred repos, daily updates☆16Sep 28, 2024Updated last year
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated last year
- Digital IC design and vlsi notes☆15Jun 24, 2020Updated 6 years ago
- ☆11Mar 4, 2022Updated 4 years ago
- SystemVerilog file list pruner☆19Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Real-Time Image Processing for ASIC/FGPA☆27Feb 23, 2022Updated 4 years ago
- TCL framework to package Vivado IP-Cores☆13May 18, 2022Updated 4 years ago
- Advanced Machine Learning Fall 2020 Project Repository☆12Dec 12, 2020Updated 5 years ago
- Distributed arithmetic (DA) is another way of implementing a dot product where one of the arrays has constant elements. The DA can be eff…☆17Aug 26, 2021Updated 5 years ago
- This Repo is meant and maintained to help learners complete the course -- "C-for-Everyone-Programming-Fundamentals-by-University-of-Calif…☆18Feb 3, 2021Updated 5 years ago
- ☆17Jan 13, 2024Updated 2 years ago
- ☆25Oct 28, 2025Updated 10 months ago
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆21Aug 10, 2023Updated 3 years ago
- Advanced Physical Design Using OpenLANE/SKY130 course notes by Ojasvi Shah☆17Oct 19, 2024Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆12Oct 17, 2024Updated last year
- ☆14Nov 8, 2023Updated 2 years ago
- Open-source RTL IP developement for IIR/FIR filters in SystemVerilog, along with the C model and verification IP in UVM☆15Jul 8, 2026Updated last month
- This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…☆28May 4, 2024Updated 2 years ago
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 8 months ago
- Interfacing OV7670 Camera module to miniSpartan6+☆12Feb 11, 2015Updated 11 years ago
- A 5-stage pipelined, rv32i core with branch prediction and hazard detection☆15Dec 11, 2025Updated 8 months ago