matsuda-slab / YOLO_ZYNQ_MASTER
Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA
☆27Updated 2 years ago
Alternatives and similar repositories for YOLO_ZYNQ_MASTER:
Users that are interested in YOLO_ZYNQ_MASTER are comparing it to the libraries listed below
- ☆51Updated last year
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆74Updated last year
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆46Updated 10 months ago
- Codes to implement MobileNet V2 in a FPGA☆24Updated 4 years ago
- HLS_YOLOV3☆23Updated last year
- YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board☆18Updated 3 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆10Updated 6 months ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- Vitis AI Lab: MNIST classifier☆17Updated 2 years ago
- ☆27Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- A DNN Accelerator implemented with RTL.☆63Updated last month
- ☆207Updated 10 months ago
- 搭建卷积神经网络并利用FPGA加速实现交通标志识别☆26Updated 4 years ago
- Implement Tiny YOLO v3 on ZYNQ☆271Updated 2 years ago
- ☆43Updated 6 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆135Updated 3 months ago
- 可运行☆29Updated 2 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated last year
- a project build the SSD net in pynq-z2☆15Updated 4 years ago
- ☆100Updated 4 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆76Updated 3 years ago
- This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…☆41Updated 3 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆135Updated last year
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆34Updated 6 months ago
- Zynq-7000 DPU TRD☆44Updated 5 years ago
- An LeNet RTL implement onto FPGA☆40Updated 6 years ago