LukiBa / zybo_yolo
YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board
☆18Updated 3 years ago
Alternatives and similar repositories for zybo_yolo:
Users that are interested in zybo_yolo are comparing it to the libraries listed below
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆28Updated 2 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR☆78Updated last year
- ☆51Updated last year
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…☆42Updated 3 months ago
- HLS_YOLOV3☆23Updated last year
- ☆29Updated 3 years ago
- 可运行☆30Updated 2 years ago
- ☆43Updated 6 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆47Updated 10 months ago
- it is a set for all the respository of the project.☆96Updated 5 years ago
- ☆15Updated 4 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- Vitis AI Lab: MNIST classifier☆17Updated 2 years ago
- ☆38Updated 3 years ago
- FPGA实现动态图像识别☆16Updated 4 years ago
- Codes to implement MobileNet V2 in a FPGA☆24Updated 4 years ago
- Zynq-7000 DPU TRD☆44Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- Implement Tiny YOLO v3 on ZYNQ☆274Updated 2 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- An AIoT project based on PYNQ-Z2 FPGA Evaluation board. Reading image from usb camera and running yolov3-tiny detection with DPU and usin…☆11Updated 2 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆76Updated 3 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆48Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆63Updated last month
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- Nuclei E203 with yolo accelerator based on xc7k325☆10Updated 7 months ago
- CNN accelerator implemented with Spinal HDL☆144Updated last year
- ☆207Updated 10 months ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago