LukiBa / zybo_yoloLinks
YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board
☆21Updated 4 years ago
Alternatives and similar repositories for zybo_yolo
Users that are interested in zybo_yolo are comparing it to the libraries listed below
Sorting:
- Implementation of YOLOv3-tiny + Depthwise Separable Convolution on FPGA☆30Updated 3 years ago
- ☆56Updated 2 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆48Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆155Updated last year
- ☆48Updated 7 years ago
- This project is to implement YOLO v3 on Xilinx FPGA with DPU☆64Updated 5 years ago
- Pynq computer vision examples with an OV5640 camera☆57Updated 5 years ago
- Implement Tiny YOLO v3 on ZYNQ☆307Updated 7 months ago
- it is a set for all the respository of the project.☆100Updated 6 years ago
- ☆33Updated 4 years ago
- ☆26Updated 3 years ago
- hls code zynq 7020 pynq z2 CNN☆88Updated 6 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆115Updated 4 years ago
- This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…☆94Updated 8 months ago
- 可运行☆39Updated 3 years ago
- HLS_YOLOV3☆25Updated last year
- ☆37Updated 4 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆66Updated last year
- FPGA accelerated TinyYOLO v2 object detection neural network☆74Updated 7 years ago
- A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA☆28Updated 4 years ago
- Codes to implement MobileNet V2 in a FPGA☆28Updated 4 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆71Updated 6 years ago
- A DNN Accelerator implemented with RTL.☆68Updated 11 months ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR☆136Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 6 years ago
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 6 years ago
- The second place winner for DAC-SDC 2020☆98Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆63Updated 3 years ago