基于FPGA量化的人脸口罩检测
☆23Aug 24, 2021Updated 4 years ago
Alternatives and similar repositories for Yolo-compression-and-deployment-in-FPGA
Users that are interested in Yolo-compression-and-deployment-in-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- HLS_YOLOV3☆26Jan 11, 2024Updated 2 years ago
- Uart transport + image processing + VGA display 基于FPGA的图像处理,包括Uart和VGA☆19Mar 10, 2020Updated 6 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆146Jul 20, 2023Updated 2 years ago
- Xilinx Kria KV260 Real-time PPE detection☆13Mar 8, 2023Updated 3 years ago
- DETR tensor去除推理过程无用辅助头+fp16部署再次加速+解决转tensorrt 输出全为0问题的新方法。☆11Jan 9, 2024Updated 2 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Semi-Supervised Unpaired Multi-Modal Learning for Label-Efficient Medical Image Segmentation☆10Jun 29, 2021Updated 4 years ago
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆16Dec 3, 2025Updated 3 months ago
- 使用FPGA实现CNN模型☆15Jun 21, 2019Updated 6 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- This repository contains an easy-to-read Python implementation of the seamless image cloning method in the paper Poisson Image Editing.☆14Aug 5, 2015Updated 10 years ago
- Canny Edge detector algorith optimized on the Programmable Logic (HW) of the Zynq-7000 FPGA Architecture☆12Jun 3, 2020Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆40Jun 27, 2021Updated 4 years ago
- CNN accelerator implemented with Spinal HDL☆158Jan 29, 2024Updated 2 years ago
- "智能公交系统电子站牌设计"毕业设计单片机和微信小程序代码☆13Jan 11, 2023Updated 3 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆11Aug 12, 2020Updated 5 years ago
- FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope☆14Sep 5, 2025Updated 6 months ago
- note about IC knowledge☆10Sep 7, 2022Updated 3 years ago
- Latent Diffusion Model-Enabled Low-Latency Semantic Communication in the Presence of Semantic Ambiguities and Wireless Channel Noises☆18Nov 19, 2024Updated last year
- [TMI'2022] SASSL☆14May 4, 2023Updated 2 years ago
- Implement Tiny YOLO v3 on ZYNQ☆312Apr 14, 2025Updated 11 months ago
- Signal generator designed with Nexy4 FPGA☆13May 14, 2023Updated 2 years ago
- Light modbus RTU Slave without SPL and HAL. This lib doesn't need timers, only UART and 2 channels of DMA.☆10Jun 25, 2019Updated 6 years ago
- it is a set for all the respository of the project.☆100Jul 23, 2019Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 9 months ago
- ☆16Dec 4, 2021Updated 4 years ago
- FPGA-Edge-Detection-Project1☆66Feb 24, 2022Updated 4 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆14Mar 10, 2019Updated 7 years ago
- stm32 HAL库使用内部RAM模拟U盘升级☆13Dec 4, 2020Updated 5 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆11Mar 12, 2021Updated 5 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆904Jul 29, 2024Updated last year
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆21Jul 7, 2024Updated last year
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals,this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 7 years ago
- 使用肤色颜色空间建模+连通域处理及分析和Harr-cascade 方法进行人脸检测。1建立多种肤色模型,结合数学形态学滤波,完成人脸检测; 2利用Matlab 自带的计算机视觉系统工具箱实现单人及多人的人脸检测。☆13Nov 23, 2018Updated 7 years ago
- YOLOv3-TensorRT-INT8-KCF is a TensorRT Int8-Quantization implementation of YOLOv3 (and YOLOv3-tiny) on NVIDIA Jetson Xavier NX Board. The…☆15Dec 20, 2021Updated 4 years ago
- Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK☆15Dec 2, 2018Updated 7 years ago
- Design of an image generator to represent a street scene. Can be used as a stand-alone design for image generator or as a test pattern ge…☆11Nov 18, 2019Updated 6 years ago
- ☆16Aug 6, 2022Updated 3 years ago
- Little RISC-V 3-stage Pipeline CPU☆16Jun 14, 2021Updated 4 years ago