thoughtpolice / rv32-sail
32-bit RISC-V Emulator
☆24Updated 6 years ago
Alternatives and similar repositories for rv32-sail
Users that are interested in rv32-sail are comparing it to the libraries listed below
Sorting:
- Haskell library for hardware description☆103Updated 5 months ago
- Galois RISC-V ISA Formal Tools☆58Updated last month
- A RiscV processor implementing the RV32I instruction set written in Clash☆53Updated 7 years ago
- Generate interface between Clash and Verilator☆22Updated last year
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- Formal specification of RISC-V Instruction Set☆100Updated 4 years ago
- ☆23Updated 3 years ago
- Kansas Lava☆47Updated 5 years ago
- A Verilog parser for Haskell.☆34Updated 3 years ago
- The Cubicle model checker☆13Updated last year
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- Build an educational formally verified version of the Nand 2 Tetris course using Coq (and other formal tools).☆55Updated 3 years ago
- ☆21Updated 9 years ago
- ☆29Updated 4 years ago
- A formal semantics of the RISC-V ISA in Haskell☆164Updated last year
- A special-purpose processor for pure, non-strict functional languages☆28Updated 4 months ago
- RISC-V BSV Specification☆20Updated 5 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated 2 months ago
- An executable specification of the RISCV ISA in L3.☆42Updated 6 years ago
- Semantic model for aspects of ELF static linking and DWARF debug information☆44Updated 5 months ago
- A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.☆58Updated 3 years ago
- Gallina to Bedrock2 compilation toolkit☆54Updated this week
- Verilog development and verification project for HOL4☆26Updated 3 weeks ago
- Iodine: Verifying Constant-Time Execution of Hardware☆12Updated 4 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated 3 weeks ago
- A language and toolset for implementing dataflow applications on FPGAs☆27Updated 6 years ago
- Intel 8080 CPU core: software emulator and CLaSH hardware description☆27Updated 2 years ago
- ☆36Updated 2 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆30Updated this week
- LLVM JIT Cycle Accurate Simulator for HardCaml☆13Updated 7 years ago