Alternatives and similar repositories for rv32-sail

Users that are interested in rv32-sail are comparing it to the libraries listed below

• blarney-lang / blarney
  Haskell library for hardware description
  ☆104Updated last month
• ku-fpg / kansas-lava
  Kansas Lava
  ☆48Updated 5 years ago
• adamwalker / clash-riscv
  A RiscV processor implementing the RV32I instruction set written in Clash
  ☆53Updated 7 years ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆60Updated 3 months ago
• cbiffle / cfm
  A 16-bit CPU and self-hosting Forth system for the Lattice ICE40 FPGA, written in Haskell.
  ☆58Updated 4 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆35Updated 4 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated 2 years ago
• benpye / nix-fpga-tools
  ☆23Updated 3 years ago
• gergoerdi / clashilator
  Generate interface between Clash and Verilator
  ☆22Updated last year
• mgajda / clash-yosys-demo
  Deploying Haskell to Lattice iCE40 using fully open source toolchain
  ☆13Updated 9 years ago
• christiaanb / contranomy
  ☆29Updated 4 years ago
• gergoerdi / clash-intel8080
  Intel 8080 CPU core: software emulator and CLaSH hardware description
  ☆27Updated 2 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆28Updated last week
• rsnikhil / Forvis_RISCV-ISA-Spec
  Formal specification of RISC-V Instruction Set
  ☆100Updated 5 years ago
• agra-uni-bremen / libriscv
  Extensible implementation of the RISC-V ISA based on FreeMonads
  ☆16Updated last year
• vegaluisjose / reticle-evaluation
  Reticle evaluation (PLDI 2021)
  ☆12Updated 4 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• braibant / Synthesis
  ☆21Updated 9 years ago
• povik / fold
  high abstraction synthesis
  ☆12Updated last year
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆13Updated 4 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆126Updated 3 years ago
• mit-plv / riscv-semantics
  A formal semantics of the RISC-V ISA in Haskell
  ☆167Updated last year
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 8 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• cucapra / patronus
  work in progress, playing around with btor2 in rust
  ☆11Updated 3 weeks ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆155Updated this week
• haflang / heron
  A special-purpose processor for pure, non-strict functional languages
  ☆28Updated 6 months ago
• Feldspar / feldspar-language
  The goal of the Feldspar project is to define a high-level language that allows description of high-performance digital signal processing…
  ☆47Updated 3 years ago
• aumouvantsillage / Vermicel-CPU-Racket
  Vermicel is a minimal RISC-V core.
  ☆9Updated last year